公开(公告)号：EP2840608A3

公开(公告)日：2015-08-05

申请号：EP14173944.1

申请日：2014-06-25

申请人： NXP B.V.

发明人： De Raad, Gijs Jan ,  Cappon, Paul Hendrik ,  Huitsing, Albert Jan

IPC分类号： H01L27/02 ,  H03K19/003 ,  H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H03K19/00315

摘要： Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.

摘要翻译： 描述了静电放电（ESD）保护装置的实施例和操作ESD保护装置的方法。 在一个实施例中，用于集成电路（IC）器件的ESD保护器件包括配置成在ESD事件期间传导ESD电流的bigFET和配置成在ESD事件期间触发bigFET的触发器器件。 所述触发器装置包括被配置为检测所述ESD事件的转换速率检测器，被配置为驱动所述bigFET的驱动器级，以及被配置为保持所述驱动器级被导通以驱动所述bigFET的栅极端子的驱动电压 这对于bigFET的漏极端子或源极端子上的预偏置不敏感。 还描述了其他实施例。

公开(公告)号：EP3001457A1

公开(公告)日：2016-03-30

申请号：EP15186224.0

申请日：2015-09-22

申请人： NXP B.V.

发明人： Huitsing, Albert Jan ,  Claes, Jan

IPC分类号： H01L27/02 ,  H01L29/417

CPC分类号： H01L27/0248 ,  H01L21/8222 ,  H01L23/367 ,  H01L23/535 ,  H01L27/0259 ,  H01L27/082 ,  H01L27/1203 ,  H01L29/41708 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a PNP ESD integrated circuit, including a substrate, an active region formed within the substrate, the active region including at least one base region of a second conductivity type, a plurality of collector regions of a first conductivity type formed within the active region, a plurality of emitter regions of the first conductivity type formed within the active region, and a local interconnect layer (LIL) contacting the plurality of emitter regions and the plurality of collector regions, the LIL including cooling fin contacts formed on the collector regions to enhance the current handling capacity of the collector regions.

摘要翻译： 公开了一种PNP ESD集成电路，包括衬底，形成在衬底内的有源区，有源区包括至少一个第二导电类型的基区，多个第一导电类型的集电区形成在有源区内 ，形成在所述有源区域内的多个第一导电类型的发射极区域以及接触所述多个发射极区域和所述多个集电极区域的局部互连层（LIL），所述LIL包括形成在所述集电极区域上的冷却鳍状触点， 提升收集区域的当前处理能力。

公开(公告)号：EP2840608B1

公开(公告)日：2017-08-30

申请号：EP14173944.1

申请日：2014-06-25

申请人： NXP B.V.

发明人： De Raad, Gijs Jan ,  Cappon, Paul Hendrik ,  Huitsing, Albert Jan

IPC分类号： H01L27/02 ,  H03K19/003 ,  H02H9/04

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H03K19/00315

公开(公告)号：EP2840608A2

公开(公告)日：2015-02-25

申请号：EP14173944.1

申请日：2014-06-25

申请人： NXP B.V.

发明人： De Raad, Gijs Jan ,  Cappon, Paul Hendrik ,  Huitsing, Albert Jan

IPC分类号： H01L27/02 ,  H03K19/003

CPC分类号： H02H9/046 ,  H01L27/0285 ,  H03K19/00315

摘要： Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.