公开(公告)号：EP1590678B1

公开(公告)日：2009-11-25

申请号：EP03777124.3

申请日：2003-12-18

申请人： NXP B.V.

发明人： SCHUTTERT, Rodger, F. ,  DE JONG, Franciscus, G., M.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318566

摘要： An integrated circuit device has boundary scan structure with a test shift register structure coupled between a test input (TDI) and the test output (TDO). The test register structure is used to shift information from the test input to a test output. Test data is transported from the input to the output by shifting. The test shift register structure contains a data shift part (106) coupled to connections (12) for a functional circuit under test. In parallel with the data shift part is an instruction shift structure (102, 104). By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or whether data travels from the test input to the test output through the data shift part. Instruction information from the instruction shift part controls operation of the device in a test mode. A sensor (14) is provided for sensing a physical operating parameter of the device. The sensor has an output (18) coupled to the shift register structure (102) for feeding a sensing result to the test output from the instruction shift part. This form of making a sensing result accessible is preferably applied to a parameter whose value is indicative of a risk of damage to the device, such as temperature. This makes it possible to detect threatening parameter values quickly.

公开(公告)号：EP1943534B1

公开(公告)日：2009-07-08

申请号：EP06809664.3

申请日：2006-10-20

申请人： NXP B.V.

发明人： ZJAJO, Amir ,  BERGVELD, Hendrik, J. ,  SCHUTTERT, Rodger, F. ,  PINEDA DE GYVEZ, Jose de Jesus

IPC分类号： G01R31/3185 ,  G01R31/317

CPC分类号： G01R31/3167 ,  G01R31/31721 ,  G01R31/318536 ,  G01R31/318575

摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.

公开(公告)号：EP0972207B1

公开(公告)日：2009-08-26

申请号：EP99900246.2

申请日：1999-01-25

申请人： NXP B.V.

发明人： DE JONG, Franciscus, G., M. ,  MURIS, Mathias, N., M. ,  SCHUTTERT, Rodger, F. ,  DE WILDE, Johannes

IPC分类号： G01R31/28 ,  G01R31/316

CPC分类号： G01R31/2853

摘要： The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (110) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (110) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing capacitance (195) between an IC pin (110) and a supply line, e.g. a ground line.

公开(公告)号：EP1943534A2

公开(公告)日：2008-07-16

申请号：EP06809664.3

申请日：2006-10-20

申请人： NXP B.V.

发明人： ZJAJO, Amir ,  BERGVELD, Hendrik, J. ,  SCHUTTERT, Rodger, F. ,  PINEDA DE GYVEZ, Jose de Jesus

IPC分类号： G01R31/3185 ,  G01R31/317

CPC分类号： G01R31/3167 ,  G01R31/31721 ,  G01R31/318536 ,  G01R31/318575

摘要： An integrated circuit (IC) comprises a plurality of analog stages (10a-c), each of the analog stages being conductively coupled to a power supply (20; 20a-c), and being conductively coupled to each other by a signal path (12); and a test arrangement for testing the plurality of analog stages, the test arrangement comprising input means such as an analog bus (40) coupled to a signal path input of each analog stage from the plurality of analog stages, output means such as a further analog bus (50) for communicating a test result to an output of the integrated circuit, switching means such as a plurality of switches (36) in the biasing infrastructure of the IC for selectively disabling an analog stage, and control means such a shift register (60) for controlling the switching means. Consequently, the analog stages of the IC can be tested and debugged in isolation without the need for switches in the signal path through the cores. A current sensor (70) may be present in the power supply to facilitate structural testing of the analog stages in isolation.

公开(公告)号：EP0807259B1

公开(公告)日：2008-04-09

申请号：EP96931947.4

申请日：1996-10-14

申请人： NXP B.V.

发明人： MURIS, Mathias, N., M. ,  DE JONG, Franciscus, G., M. ,  DE WILDE, Johannes ,  SCHUTTERT, Rodger, F.

IPC分类号： G01R31/28

CPC分类号： G01R31/3167 ,  G01R31/2882 ,  G01R31/31855 ,  G01R31/318594

摘要： A testable circuit comprises a signal path having a time-dependent response behavior (for example, a high-pass filter behavior). The signal path is tested for faults. To this end, the circuit is switched to a test mode in which the signal path is isolated from other signal paths. Subsequently, a test signal containing a signal transition is applied to the input of the signal path and it is tested whether the signal on the output of the signal path at any instant exceeds a threshold level during a predetermined time interval after the transition. The result is loaded into a register and read from the circuit.