公开(公告)号：EP1706751B1

公开(公告)日：2008-02-20

申请号：EP04806590.8

申请日：2004-12-20

申请人： NXP B.V.

发明人： DE WILDE, Johannes ,  PINEDA DE GYVEZ, Jose, D., J. ,  DE JONG, Franciscus, G., M. ,  HUISKEN, Josephus, A. ,  BOEVE, Hans, M., B. ,  PHAN LE, Kim

IPC分类号： G01R31/30 ,  G01R33/09 ,  G01R15/20 ,  G11C11/15

CPC分类号： G01R31/3004 ,  G01R15/20 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675

公开(公告)号：EP1590678B1

公开(公告)日：2009-11-25

申请号：EP03777124.3

申请日：2003-12-18

申请人： NXP B.V.

发明人： SCHUTTERT, Rodger, F. ,  DE JONG, Franciscus, G., M.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318566

摘要： An integrated circuit device has boundary scan structure with a test shift register structure coupled between a test input (TDI) and the test output (TDO). The test register structure is used to shift information from the test input to a test output. Test data is transported from the input to the output by shifting. The test shift register structure contains a data shift part (106) coupled to connections (12) for a functional circuit under test. In parallel with the data shift part is an instruction shift structure (102, 104). By means of test control signals it is controlled whether instruction information travels from the test input to the test output through the instruction shift part or whether data travels from the test input to the test output through the data shift part. Instruction information from the instruction shift part controls operation of the device in a test mode. A sensor (14) is provided for sensing a physical operating parameter of the device. The sensor has an output (18) coupled to the shift register structure (102) for feeding a sensing result to the test output from the instruction shift part. This form of making a sensing result accessible is preferably applied to a parameter whose value is indicative of a risk of damage to the device, such as temperature. This makes it possible to detect threatening parameter values quickly.

公开(公告)号：EP1417502B1

公开(公告)日：2007-10-17

申请号：EP02749176.0

申请日：2002-07-09

申请人： NXP B.V.

发明人： BIEWENGA, Alexander, S. ,  VAN DE LOGT, Leon, M., A. ,  DE JONG, Franciscus, G., M. ,  LOUSBERG, Guillaume, E., A.

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G11C29/025 ,  G01R31/318547 ,  G11C29/02 ,  G11C2029/3602

摘要： An integrated circuit is switchable between a normal operating mode and a test mode. A functional circuit and a test pattern converter are both coupled between input contacts, output contacts and a redefinable contact of the integrated circuit. In the test mode respectively the test pattern converter drives the outputs contacts and, dependent on the circuit configuration, the redefinable contact. The test pattern converter is arranged to provide a first and second relation between signals at the input contacts and the output contacts, with the redefinable contact used as an input or output contact respectively, dependent on the circuit configuration. The relations have been selected so as to permit testing of stuck-at and cross-connect errors with the redefinable contact used as input and output contact respectively.

公开(公告)号：EP0972207B1

公开(公告)日：2009-08-26

申请号：EP99900246.2

申请日：1999-01-25

申请人： NXP B.V.

发明人： DE JONG, Franciscus, G., M. ,  MURIS, Mathias, N., M. ,  SCHUTTERT, Rodger, F. ,  DE WILDE, Johannes

IPC分类号： G01R31/28 ,  G01R31/316

CPC分类号： G01R31/2853

摘要： The invention relates to a method of testing interconnections in integrated circuit (IC) assemblies. Hereto, a test signal is applied to an IC pin (110) providing an input terminal to the interconnection. In known methods, such as the boundary-scan method, a response signal is measured on an output terminal of the interconnection, provided by a further IC pin. According to the invention, however, a response signal is evaluated which is generated on the same terminal (110) as to which the test signal is applied. This has the advantage that the method of the invention can be applied when only one end of the interconnect to be tested can be supplied with appropriate test hardware. The method is particularly suited for testing capacitance (195) between an IC pin (110) and a supply line, e.g. a ground line.

公开(公告)号：EP1521974B1

公开(公告)日：2008-08-27

申请号：EP03738449.2

申请日：2003-06-20

申请人： NXP B.V.

发明人： VAN DE LOGT, Leon, M., A. ,  DE JONG, Franciscus, G., M.

IPC分类号： G01R31/3185 ,  G01R31/316

CPC分类号： G11C29/022 ,  G01R31/2853 ,  G01R31/3185 ,  G01R31/31855 ,  G11C29/02 ,  G11C29/025

摘要： A test arrangement for testing the interconnections of an electronic circuit ( 100 ) and a further electronic circuit is provided. A first selection of I/O nodes ( 120 ), which are arranged to receive input data in a functional mode of the electronic circuit ( 100 ), and which are coupled to a test unit in a test mode of the electronic circuit ( 100 ). The test unit has a combinatorial circuit ( 160 ) for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes ( 120 ) and a second selection of I/O nodes ( 130 ) via logic gates ( 141-144 ). These interconnections increase the interconnect test coverage of the electronic device ( 100 ), because the interconnects with the further electronic circuits that are associated with I/O nodes ( 131-134 ) become testable as well.

公开(公告)号：EP0807259B1

公开(公告)日：2008-04-09

申请号：EP96931947.4

申请日：1996-10-14

申请人： NXP B.V.

发明人： MURIS, Mathias, N., M. ,  DE JONG, Franciscus, G., M. ,  DE WILDE, Johannes ,  SCHUTTERT, Rodger, F.

IPC分类号： G01R31/28

CPC分类号： G01R31/3167 ,  G01R31/2882 ,  G01R31/31855 ,  G01R31/318594

摘要： A testable circuit comprises a signal path having a time-dependent response behavior (for example, a high-pass filter behavior). The signal path is tested for faults. To this end, the circuit is switched to a test mode in which the signal path is isolated from other signal paths. Subsequently, a test signal containing a signal transition is applied to the input of the signal path and it is tested whether the signal on the output of the signal path at any instant exceeds a threshold level during a predetermined time interval after the transition. The result is loaded into a register and read from the circuit.