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    CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT
    4.
    发明公开
    CIRCUITRY TO PREVENT PEAK POWER PROBLEMS DURING SCAN SHIFT 有权
    电路用于防止EXCELLENCE问题在扫描转移期间

    公开(公告)号：EP2122378A1

    公开(公告)日：2009-11-25

    申请号：EP08705457.3

    申请日：2008-01-02

    申请人： Silicon Image, Inc.

    发明人： SUL, Chinsong ,  KIM, Heon

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318575 ,  G01R31/318594

    摘要： In some embodiments, In some embodiments, a chip includes first and second scan chain segments each including registers and multiplexers to provide to the registers scan input signals during scan input periods and captured output signals during a capture periods. The chip also includes circuitry to provide first and second test clock signals to the registers of the first and second scan chain segments, respectively, wherein the second test clock signal is provided by a different signal path in the circuitry during the scan input periods than during the capture periods, and during the scan input periods the second test clock signal is skewed with respect to the first test clock signal. Other embodiments are described and claimed.

    LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST
    5.
    发明公开
    LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST 有权
    LOGIC的系统和方法用于支持扫描测试

    公开(公告)号：EP2030032A2

    公开(公告)日：2009-03-04

    申请号：EP07784466.0

    申请日：2007-06-18

    申请人： QUALCOMM Incorporated

    发明人： SAINT-LAURENT, Martin ,  BASSETT, Paul ,  PATEL, Prayag

    IPC分类号： G01R31/3185

    CPC分类号： G01R31/318552 ,  G01R31/3025 ,  G01R31/318575

    摘要： A logic device includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

    SCAN TEST DESIGN METHOD, SCAN TEST CIRCUIT, SCAN TEST CIRCUIT INSERTION CAD PROGRAM, LARGE-SCALE INTEGRATED CIRCUIT, AND MOBILE DIGITAL DEVICE
    6.
    发明公开
    SCAN TEST DESIGN METHOD, SCAN TEST CIRCUIT, SCAN TEST CIRCUIT INSERTION CAD PROGRAM, LARGE-SCALE INTEGRATED CIRCUIT, AND MOBILE DIGITAL DEVICE 有权
    SCAN TEST设计过程中，扫描测试电路，扫描TESTSCHALTUNGSEINFÜGECAD程序HIGH集成电路和移动数字设备

    公开(公告)号：EP1643257A1

    公开(公告)日：2006-04-05

    申请号：EP04747555.3

    申请日：2004-07-08

    申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

    发明人： HOSHAKU, Masahiro

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318575 ,  G01R31/318591 ,  G01R31/318594

    摘要： In scan test circuit design, a plurality of flipflop circuits (102a, 102b or 102c) driven with each of final-stage elements 101f of a clock tree T are connected in series, to form a sub-scan chain. Also, sub-scan chains smallest in the relative difference in the number of stages of delay elements existing from the clock supply point S of the clock tree T (i.e., sub-scan chains different by one stage) are connected to each other. Further, sub-scan chains are connected so that data shift be made from a flipflop circuit larger in clock delay to a flipflop circuit smaller in clock delay. This reduces the number of delay elements inserted in data lines of a shift register for hold time guarantee in shift operation of the scan shift register, and suppresses power consumption.

    摘要翻译： 在扫描测试的电路设计，每个末级元件的驱动101F的时钟树T的触发器电路（102A，102B或102c）的一个多元化串联连接，以形成一个子扫描链。 所以副扫描链最小在从时钟树T的时钟供给点S现有的延迟元件的级数的相对差（即，通过一个阶段不同的子扫描链）连接到海誓山盟。 此外，象数据移位从一个触发器电路在时钟延迟小的触发器电路在时钟延迟大作出副扫描链被连接。 这减少了插入在扫描移位寄存器的移位操作的保持时间保证的移位寄存器的数据线的延迟元件的数目，并且抑制电力消耗。