公开(公告)号：EP2533204B1

公开(公告)日：2018-06-20

申请号：EP12181630.0

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： H04N19/176 ,  H04N19/50 ,  H04N19/172 ,  H04N19/46 ,  H04N19/13 ,  H04N19/12 ,  H04N19/156 ,  H04N19/174

CPC分类号： H04N19/12 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video encoding apparatus with a guarantee of a fixed processing time comprises a encoding unit (41) for performing an arithmetic decoding process with context modeling on the video signal; and a controlling unit (45, 46) for controlling the arithmetic encoding process so as to terminate the arithmetic encoding process and to maintain a context value previously used in the arithmetic encoding process in case of outputting raw data of the video signal as a bit stream and for inserting a bit subjected to a terminal process of the arithmetic encoding process into the bit stream.

公开(公告)号：EP2535870B1

公开(公告)日：2018-05-16

申请号：EP12184197.7

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： H04N19/176 ,  H04N19/50 ,  H04N19/172 ,  H04N19/46 ,  H04N19/13 ,  H04N19/12 ,  H04N19/156 ,  H04N19/174

CPC分类号： H04N19/12 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video encoding apparatus with a guarantee of a fixed processing time comprises a encoding unit (41) for performing an arithmetic decoding process with context modeling on the video signal; and a controlling unit (45, 46) for controlling the arithmetic encoding process so as to terminate the arithmetic encoding process and to maintain a context value previously used in the arithmetic encoding process in case of outputting raw data of the video signal as a bit stream and for inserting a bit subjected to a terminal process of the arithmetic encoding process into the bit stream.

公开(公告)号：EP2635028A2

公开(公告)日：2013-09-04

申请号：EP13169720.3

申请日：2010-02-12

申请人： Sony Corporation

发明人： Nakagami, Ohji ,  Yagasaki, Yoichi

IPC分类号： H04N7/26 ,  H04N7/32 ,  H04N7/34 ,  H04N7/36 ,  H04N7/46 ,  H04N7/50

CPC分类号： H04N19/159 ,  H04N19/105 ,  H04N19/107 ,  H04N19/109 ,  H04N19/117 ,  H04N19/503 ,  H04N19/51 ,  H04N19/513 ,  H04N19/573 ,  H04N19/577 ,  H04N19/593 ,  H04N19/615 ,  H04N19/63 ,  H04N19/82

摘要： The present invention relates to an image processing apparatus and method that can generate a high-accuracy prediction image with a small amount of control information. A motion compensation circuit (51) specifies a macroblock corresponding to a prediction image in a reference frame other than a current frame using a motion vector supplied from a prediction mode determination circuit (41). The motion compensation circuit (51) reads an image of the specified macroblock from a frame memory (19), and extracts the read image as a motion compensation image. An intra-prediction circuit (52) performs intra-prediction on the current frame using an arbitrary method to generate an intra-prediction image IP. The present invention can be applied to, for example, an encoding apparatus and a decoding apparatus.

摘要翻译： 本发明涉及能够以少量控制信息生成高精度预测图像的图像处理装置和方法。 运动补偿电路（51）使用从预测模式确定电路（41）提供的运动矢量来指定与除了当前帧之外的参考帧中的预测图像相对应的宏块。 运动补偿电路（51）从帧存储器（19）读取指定宏块的图像，并且提取读取的图像作为运动补偿图像。 帧内预测电路（52）使用任意方法对当前帧执行帧内预测以生成帧内预测图像IP。 本发明可以应用于例如编码装置和解码装置。

公开(公告)号：EP2627089A3

公开(公告)日：2013-08-21

申请号：EP13166271.0

申请日：2003-04-22

申请人： Sony Corporation

发明人： Sato, Kazushi ,  Suzuki, Teruhiko ,  Sunohara, Osamu ,  Yagasaki, Yoichi

IPC分类号： H04N7/26 ,  H03M7/40

CPC分类号： H04N19/52 ,  H03M7/4006 ,  H04N19/13 ,  H04N19/16 ,  H04N19/176 ,  H04N19/513 ,  H04N19/537

摘要： The present invention relates to, for example, an encoding apparatus and an encoding method, a decoding apparatus and a decoding method, a recording medium, and a program suitable for encoding image signals with a higher compression ratio for transmission or accumulation. In an arithmetic coding section (5 8), from among the syntax elements of input image compression information, the frame/field flag is first encoded by a frame/field flag context model (91). When the macroblock to be processed is subjected to frame-based encoding, a frame-based context model (92), specified in the current H.26L standard, is applied. On the other hand, when the macroblock to be processed is subjected to field-based encoding, a field-based context model (94) is applied for the syntax elements described below. The present invention is applied to an encoder for encoding image information and a decoder for decoding image information.

公开(公告)号：EP2624461A3

公开(公告)日：2013-08-21

申请号：EP13164839.6

申请日：2003-04-22

申请人： Sony Corporation

发明人： Sato, Kazushi ,  Suzuki, Teruhiko ,  Sunohara, Osamu ,  Yagasaki, Yoichi

IPC分类号： H03M7/40 ,  H04N7/26

CPC分类号： H04N19/52 ,  H03M7/4006 ,  H04N19/13 ,  H04N19/16 ,  H04N19/176 ,  H04N19/513 ,  H04N19/537

摘要： The present invention relates to, for example, an encoding apparatus and an encoding method, a decoding apparatus and a decoding method, a recording medium, and a program suitable for encoding image signals with a higher compression ratio for transmission or accumulation. In an arithmetic coding section (58), from among the syntax elements of input image compression information, the frame/field flag is first encoded by a frame/field flag context model (91). When the macroblock to be processed is subjected to frame-based encoding, a frame-based context model (92), specified in the current H.26L standard, is applied. On the other hand, when the macroblock to be processed is subjected to field-based encoding, a field-based context model (94) is applied for the syntax elements described below. The present invention is applied to an encoder for encoding image information and a decoder for decoding image information.

公开(公告)号：EP2533204A3

公开(公告)日：2013-02-27

申请号：EP12181630.0

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： G06T9/00 ,  H04N7/30 ,  H04N7/50 ,  H04N7/26

CPC分类号： H04N19/12 ,  H04N19/00569 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video decoding apparatus with a guarantee of a fixed processing time comprises a decoding unit (82) for performing an arithmetic decoding process with context modeling on a bit stream including raw data of a video signal and a controlling unit (81, 84, 85) for controlling the arithmetic decoding process so as to terminate the arithmetic decoding process in case of decoding the raw data.

公开(公告)号：EP2535870A2

公开(公告)日：2012-12-19

申请号：EP12184197.7

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： G06T9/00 ,  H04N7/30 ,  H04N7/50 ,  H04N7/26

CPC分类号： H04N19/12 ,  H04N19/00569 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video decoding apparatus with a guarantee of a fixed processing time comprises a receiving unit for receiving a bit subjected to a terminal process of an arithmetic encoding process with context modeling from the bit stream; a decoding unit (82) for performing an arithmetic decoding process with context modeling on the bit stream including the raw data; and a controlling unit (81, 84, 85) for controlling the arithmetic decoding process so as to terminate the arithmetic decoding process and to maintain a context value previously used in the arithmetic decoding process in case of receiving the bit subj ected to the terminal process and decoding the raw data.

摘要翻译： 具有固定处理时间的保证的视频解码装置包括：接收单元，用于从比特流接收经历具有上下文建模的算术编码处理的终端处理的比特; 解码单元，用于对包含所述原始数据的比特流进行具有上下文建模的算术解码处理; 以及控制单元（81,84,85），用于控制算术解码处理，以便终止算术解码处理，并且在接收到被终止处理的比特的情况下维持先前在算术解码处理中使用的上下文值 并解码原始数据。

公开(公告)号：EP2533208A2

公开(公告)日：2012-12-12

申请号：EP12181638.3

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： G06T9/00 ,  H04N7/30 ,  H04N7/50 ,  H04N7/26

CPC分类号： H04N19/12 ,  H04N19/00569 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video encoding apparatus with a guarantee of a fixed processing time comprises a encoding unit (41) for performing an arithmetic decoding process with context modeling on the video signal; and a controlling unit (45, 46) for controlling the arithmetic decoding process so as to terminate the arithmetic encoding process and to maintain a context value previously used in the arithmetic encoding process in case of outputting raw data of the video signal as a bit stream.

摘要翻译： 一种具有固定处理时间保证的视频编码设备包括：编码单元（41），用于对视频信号进行具有上下文建模的算术解码处理; 以及控制单元（45,46），用于控制算术解码处理，以便在输出视频信号的原始数据作为比特流的情况下终止算术编码处理并保持在算术编码处理中先前使用的上下文值 。

公开(公告)号：EP2533206A2

公开(公告)日：2012-12-12

申请号：EP12181633.4

申请日：2003-10-09

申请人： Sony Corporation

发明人： Yagasaki, Yoichi ,  Sunohara, Osamu ,  Murayama, Jun

IPC分类号： G06T9/00 ,  H04N7/30 ,  H04N7/50 ,  H04N7/26

CPC分类号： H04N19/12 ,  H04N19/00569 ,  H04N19/13 ,  H04N19/156 ,  H04N19/172 ,  H04N19/174 ,  H04N19/176 ,  H04N19/46 ,  H04N19/50

摘要： A video encoding apparatus with a guarantee of a fixed processing time comprises a encoding unit (41) for performing an arithmetic encoding process with context modeling on the video signal; and a controlling unit (45, 46) for controlling the arithmetic encoding process so as to maintain a context value previously used in the arithmetic encoding process in case of outputting raw data of the video signal as a bit stream.

摘要翻译： 一种具有固定处理时间保证的视频编码设备包括：编码单元（41），用于对视频信号执行具有上下文建模的算术编码处理; 以及控制单元（45,46），用于控制算术编码处理，以便在输出视频信号的原始数据作为比特流的情况下，保持先前在算术编码处理中使用的上下文值。

公开(公告)号：EP2276259B1

公开(公告)日：2012-08-22

申请号：EP10011843.9

申请日：1994-03-01

申请人： Sony Corporation

发明人： Suzuki, Teruhiko ,  Yagasaki, Yoichi ,  Sudo, Tatsuya ,  Okazaki, Toru

IPC分类号： H04N7/30 ,  H04N9/804 ,  H04N7/26

CPC分类号： G06F17/147 ,  H04N19/124 ,  H04N19/126 ,  H04N19/18 ,  H04N19/42 ,  H04N19/45 ,  H04N19/60 ,  H04N19/61 ,  H04N19/65 ,  H04N19/85 ,  H04N19/89