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526 条记录 (耗时 0.015 秒)

    INTERFACE SYSTEM
    4.
    发明公开
    INTERFACE SYSTEM 审中-公开

    公开(公告)号：EP4235362A3

    公开(公告)日：2023-09-27

    申请号：EP23175032.4

    申请日：2017-09-08

    申请人： Kioxia Corporation

    发明人： Saito, Toshitada ,  Fujimoto, Akihisa

    IPC分类号： G06F13/42 ,  G06F1/32 ,  G06F13/16 ,  H04L7/033 ,  G06F1/04 ,  G06F1/12 ,  H04L7/00 ,  G06F1/3237 ,  H03L7/07 ,  H03L7/091 ,  H04L25/08 ,  H04L25/14

    摘要： According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

    METHOD AND APPARATUS FOR ALIGNMENT DELAY COMPENSATION
    5.
    发明公开
    METHOD AND APPARATUS FOR ALIGNMENT DELAY COMPENSATION 审中-公开

    公开(公告)号：EP4243307A1

    公开(公告)日：2023-09-13

    申请号：EP23159959.8

    申请日：2023-03-03

    申请人： Nokia Solutions and Networks Oy

    发明人： TANG, Shi Qing ,  HUANG, Lei ,  LIU, Da Lin

    IPC分类号： H04J3/06 ,  H04L25/14 ,  H04L43/0852

    摘要： The objective of the embodiments of the present application is to provide a method and apparatus for alignment delay compensation. Said method comprises: detecting on the receiver side the alignment delay caused by the shifting of data to the correct alignment position in the physical coding sublayer; transmitting the detected alignment delay to the transmitting side via cross-connect; performing delay compensation on the transmitting side based on said alignment delay. The embodiments of the present application has the following advantages: with the method for alignment delay compensation in physical coding sublayer in accordance with the embodiments of the present application, by detecting the alignment delay in the physical coding sublayer on the receiver side, transmitting the alignment delay to the transmitting side, and performing delay compensation on the transmitting side, the asymmetric delay in the front-haul network can be compensated for, and the accuracy of delay compensation can be greatly improved; a low-cost way of ensuring equal delay for all the ports, especially for the ports in the uplink and downlink data links, is provided.

    N-PHASE POLARITY OUTPUT PIN MODE MULTIPLEXER
    9.
    发明公开
    N-PHASE POLARITY OUTPUT PIN MODE MULTIPLEXER 审中-公开

    公开(公告)号：EP3826248A1

    公开(公告)日：2021-05-26

    申请号：EP21150198.6

    申请日：2013-07-01

    申请人： QUALCOMM INCORPORATED

    发明人： WILEY, GEORGE A. ,  RASKIN, Glenn D. ,  LEE, Chulkyu

    IPC分类号： H04L25/02 ,  H04L25/14 ,  H04L25/49 ,  H04L25/493 ,  G06F13/38 ,  H04L5/14 ,  H04L5/16

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.