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    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS
    6.
    发明公开
    MULTI-WIRE SIGNALING WITH MATCHED PROPAGATION DELAY AMONG WIRE PAIRS 审中-公开
    多线信号在线对中具有匹配传播延迟

    公开(公告)号：EP3162012A1

    公开(公告)日：2017-05-03

    申请号：EP15738526.1

    申请日：2015-06-23

    申请人： Qualcomm Incorporated

    发明人： PANDEY, Shree Krishna ,  KUNDU, Arun Chandra ,  WILEY, George Alan ,  LEE, Chulkyu

    IPC分类号： H04L25/02

    CPC分类号： H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

    摘要： In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

    摘要翻译： 在包括至少三根导线的多导线通道中，多导线通道的每对唯一导线对具有大致相同的信号传播时间。 通过这种方式，可以在多线信道中缓解抖动，用于发送信号，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每个其他导线都是浮动的。 在一些实现中，信号传播时间的匹配涉及为至少一个导线提供附加延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供附加延迟。

    VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS
    8.
    发明公开
    VOLTAGE MODE DRIVER CIRCUIT FOR N-PHASE SYSTEMS 有权
    电压模式驱动器电路是否N相系统

    公开(公告)号：EP2965216A1

    公开(公告)日：2016-01-13

    申请号：EP14713350.8

    申请日：2014-03-07

    申请人： Qualcomm Incorporated

    发明人： LEE, Chulkyu ,  WILEY, George Alan ,  SENGOKU, Shoichiro

    IPC分类号： G06F13/40

    CPC分类号： H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

    N-PHASE POLARITY OUTPUT PIN MODE MULTIPLEXER
    9.
    发明公开
    N-PHASE POLARITY OUTPUT PIN MODE MULTIPLEXER 审中-公开
    复用器PIN模式N相性输出

    公开(公告)号：EP2868046A1

    公开(公告)日：2015-05-06

    申请号：EP13741905.7

    申请日：2013-06-28

    申请人： Qualcomm Incorporated

    发明人： WILEY, George Alan ,  RASKIN, Glenn D. ,  LEE, Chulkyu

    IPC分类号： H04L25/02

    CPC分类号： H04L25/02 ,  G06F13/385 ,  H04L5/1423 ,  H04L5/16 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/4923 ,  H04L25/493

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as
    N -phase polarity encoded symbols or as packets on differentially driven connectors. A desired operational mode for communicating between the two devices is determined, an encoder is selected to drive a plurality of connectors communicatively coupling the two devices, and a plurality of drivers is configured to receive encoded data from the encoder and drive the plurality of connectors. Switches may couple outputs of the selected encoder to the plurality of drivers. One or more outputs of another encoder may be caused or forced to enter a high impedance mode.