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">91.发明公开An arbitration unit with circular or "round-robin" priority, particularly for multiprocessor systems with synchronous symmetrical processors 失效仲裁优先级具有圆形，特别是用于与同步对称的处理器的多处理器系统
公开(公告)号：EP0782081A1
公开(公告)日：1997-07-02
申请号：EP95830560.9
申请日：1995-12-29
发明人： Zulian, Ferruccio
IPC分类号： G06F13/364
CPC分类号： G06F13/364
摘要： In a synchronous arbitration unit with circular (round-robin) priority for arbitrating between N requests (Ri) for access to common resources of a multiprocessor system, the requests (Ri) stabilized in an input register (40) timed by a clock signal (CLK1) are applied as inputs to a fixed-priority arbitration network (44) having 2N-1 inputs, N-1 of the requests being applied both to a first set of N-1 lower-priority inputs of the network and, through masking circuits (42) which selectively mask the requests with a binary masking configuration generated by mask-generating circuits (43) in accordance with predetermined priority-rotation criteria, to a second set of N-1 higher-priority inputs of the network, in the same order of input priority. The grant signals output by the network are latched in an output register (41) after logical OR of the grant signals associated with the same request and the arbitration unit thus formed has a minimal arbitration time and is constituted by a small number of logic components.
摘要翻译： 与用于访问多处理器系统的公共资源N个请求（RI）之间进行仲裁圆形（循环）的优先级的同步仲裁单元，所述请求（RI）在由时钟信号定时输入寄存器（40）稳定化在（ CLK1）被施加作为输入到具有2N-1个输入端的固定优先级仲裁网络（44），N-1的请求被同时适用于第一组的网络的N-1优先级较低的输入，并通过掩蔽 电路（42），其选择性地掩蔽与由雅舞蹈掩模产生电路（43）具有预定优先级的旋转的标准生成的二进制掩蔽构成的请求，第二组的网络的N-1高优先级的输入，在 相同的顺序优先级的输入。 由网络输出的许可信号在输出寄存器（41）后，用同样的请求，并由此形成的仲裁单元相关联的授权信号的逻辑OR锁存具有最小仲裁时间并且由少数的逻辑部件构成。
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公开(公告)号：EP0437712B1
公开(公告)日：1997-04-02
申请号：EP90122942.7
申请日：1990-11-30
发明人： Zulian, Ferruccio
IPC分类号： G06F12/08
CPC分类号： G06F9/3814 , G06F9/3802 , G06F12/0859 , G06F12/0862 , G06F12/0897
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公开(公告)号：EP0744683A1
公开(公告)日：1996-11-27
申请号：EP95830216.8
申请日：1995-05-22
摘要： A constant voltage drop voltage regulator for low power dissipation electronic systems which, from a first regulated supply voltage (V1) on the order of few volts, obtains a second regulated supply voltage (V2) (having the same regulating characteristics as the first in absolute value) a predetermined fraction of a volt lower than the first, by means of a MOSFET (1) in series between the input (2) and the output (4) of the regulator, the conductivity of the MOSFET (1) being varied by a control circuit (5) which is powered from a voltage multiplier (12) at a voltage (VT) multiple of the first voltage (V1), by comparison of the voltage drop due to the MOSFET (1) and suitably amplified with a predetermined reference voltage (VREF), the comparison error, as amplified with a high gain, being applied as a control signal to the gate electrode of the MOSFET (1).
摘要翻译： 一种用于低功耗电子系统的恒定电压降电压调节器，其从几伏数量级的第一稳压电源电压（V1）获得第二稳压电源电压（V2）（具有与绝对值相同的调节特性） 值）通过串联在调节器的输入（2）和输出（4）之间的MOSFET（1），比第一个电压低的伏特的预定分数，MOSFET（1）的导电率由 通过比较由MOSFET（1）引起的电压降并以预定的电压（V1）进行适当放大的，以第一电压（V1）的倍数的电压（VT）由倍压器（12）供电的控制电路（5） 参考电压（VREF），作为控制信号被施加到MOSFET（1）的栅电极的以高增益放大的比较误差。
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94.发明公开Endless ink ribbon cartridge with protected ribbon splice, and a protection arrangement therefor 失效Endlostintenbandkassette mit Bandspleissschutzvorrichtung und Schutzanordnungdafür
公开(公告)号：EP0713783A1
公开(公告)日：1996-05-29
申请号：EP94830549.5
申请日：1994-11-25
发明人： Cavagnolo, Gianpaolo
IPC分类号： B41J33/10
摘要： An endless ink ribbon (2) cartridge (1,3,4,11) with protected splice (23) of the endless ribbon, wherein a reactance detector element (28,29,65) housed in the cartridge (1,3,4,11) at a location close to a predetermined travel path of the ink ribbon (2) increases its reactance as a conductive strip (34,68) disposed on the ribbon (2) at a predetermined location relative to the splice (23) moves close past the detector element (28,29,65), the reactance increase being detected by a protection arrangement (56,43,46,47,48,51,52,53,57,58) external of the cartridge to prevent printing operations from being carried out through said splice (23).
摘要翻译： 具有环形带的受保护接头（23）的无端墨带（2）盒（1,3,4,11），其中容纳在盒（1,3,4）中的电抗检测器元件（28,29,65） ，11）在靠近墨带（2）的预定行进路径的位置处增加其作为在相对于接头（23）移动的预定位置处设置在色带（2）上的导电条（34,68）的电抗 靠近检测器元件（28,29,65），电抗增加由盒外部的保护装置（56,43,46,47,48,51,52,53,57,58）检测，以防止打印 通过所述接头（23）进行的操作。
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95.发明公开Resolution transforming raster based imaging system and related transformation method 失效AuflösungsumsetzendesRasterabbildungssystem und entsprechendes Umsetzungsverfahren。
公开(公告)号：EP0678827A1
公开(公告)日：1995-10-25
申请号：EP94830159.3
申请日：1994-03-31
发明人： Zulian, Ferruccio , Zulian, Ajmone
CPC分类号： G06K15/128 , G06K15/1223
摘要： Resolution transforming raster based imaging system where an image is formed by displaying dots arranged along scan lines, scanned by an energization beam. The scan lines have a predetermined resolution, for example 300 dpi. The image bit map is stored with a row resolution multiple of said predetermined resolution, for example 600 dpi. Only a subset of the rows stored in the bit map is related to the scan lines. The size of the dots being displaced depends both on the value of a central bit in row related to a scan line and on the valves of the bits surrounding said central bit.
摘要翻译： 通过显示通过激励光束扫描的沿着扫描线排列的点来形成通过形成图像的基于光栅的成像系统的分辨率。 扫描线具有预定分辨率，例如300dpi。 图像位图以所述预定分辨率的行分辨率倍数存储，例如600dpi。 只有存储在位图中的行的一部分与扫描线相关。 被移位的点的大小取决于与扫描线相关的行中的中心位的值以及围绕所述中心位的位的阀。
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公开(公告)号：EP0332911B1
公开(公告)日：1995-02-08
申请号：EP89103358.1
申请日：1989-02-25
发明人： Maccianti, Tiziano , Oldani, Angelo
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
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97.发明授权Data processing system having dual arbiter for controlling access to a system bus 失效具有Zweiwegarbiter用于控制访问系统总线的数据处理系统。
公开(公告)号：EP0399204B1
公开(公告)日：1994-10-19
申请号：EP90107202.5
申请日：1990-04-17
IPC分类号： G06F13/364
CPC分类号： G06F13/364
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98.发明公开A multi-processor system with shared memory 失效Multiprozessorsystem mit gemeinschaftlichem Speicher。
公开(公告)号：EP0608663A1
公开(公告)日：1994-08-03
申请号：EP93830022.5
申请日：1993-01-25
CPC分类号： G06F13/1663 , G06F15/167 , G06F15/8015
摘要： A multi-processor system in which a plurality of processors (1, 2, 3, 4) have access to a plurality of shared memory modules (10, 11, 12, 113, 114), comprising a memory control unit (15), interconnection logic circuits (16), a system bus (17) for the multipoint connection of the processors to the memory control unit (15) and for the transfer of memory addresses and commands for ordered and successive read/write operations via the system bus (17) and the memory control unit (15), whilst the transfer of data to and from the memory modules takes place through data channels (I/OD(i)) which connect the various processors (1, 2, 3, 4) on a point-to-point basis to the interconnection logic circuits (16) and via these to a memory data transfer channel (19).
摘要翻译： 一种多处理器系统，其中多个处理器（1,2,3,4）能够访问多个共享存储器模块（10,11,12,133,114），包括存储器控制单元（15）， 互连逻辑电路（16），用于处理器到存储器控制单元（15）的多点连接的系统总线（17），以及用于经由系统总线（32）的有序和连续读/写操作的存储器地址和命令的传送（ 17）和存储器控制单元（15），同时通过将各种处理器（1,2,3,4）连接到数据通道（I / OD（i））上的数据通道（I / OD（i）） 基于点到点的互连逻辑电路（16）并经由这些到存储器数据传输通道（19）。
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公开(公告)号：EP0401585B1
公开(公告)日：1994-07-13
申请号：EP90109625.5
申请日：1990-05-21
IPC分类号： H01R13/627 , H01R13/639
CPC分类号： H01R13/6273
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公开(公告)号：EP0578901A1
公开(公告)日：1994-01-19
申请号：EP92830385.8
申请日：1992-07-16
发明人： Fare', Carlo
CPC分类号： G03G15/657 , G03G15/2028 , G03G15/6582 , G03G2215/00413
摘要： Electrophotographic printing apparatus where the toner image is transferred to the underside of a paper sheet and where the paper sheet is guided from a transfer station (B) to a fixing unit entrance (A), by a grid plate to which the paper sheet adheres owing to suction means (10), the grid plate forming a guiding surface extending from the transfer station towards the fixing unit entrance, and diverging from the plane defined by the transfer station and the fixing unit entrance of an angle such that the path followed by the paper from the transfer station to the entrance of the fixing unit is slighty greater than their distance, whereby allowance is provided for paper contractions and undersired paper tensioning is prevented.
摘要翻译： 电子照相打印设备，其中调色剂图像被转印到纸张的下侧，并且纸张从传送站（B）被引导到定影单元入口（A），通过纸张粘附到的格栅板 到抽吸装置（10），所述格栅板形成从所述传送站朝向所述固定单元入口延伸的引导表面，并且从由所述传送站限定的平面和所述固定单元入口以一定角度发散， 从转运站到定影单元入口的纸张比距离大一点，由此可以提供纸张收缩的余量，防止纸张张力过低。
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