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    Memory reconfiguration method in a data processing system
    1.
    发明公开
    Memory reconfiguration method in a data processing system 失效
    数据处理系统中的内存重新配置方法

    公开(公告)号：EP0108346A2

    公开(公告)日：1984-05-16

    申请号：EP83110751.1

    申请日：1983-10-27

    申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.

    发明人： Mantellina, Calogero ,  Trivella, Roberto ,  Quadraruopolo, Andrea

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0684 ,  G06F12/0653

    摘要： Memory mapping method in a data processing system wherein the memory comprises a plurality of modules having a capacity variable by multiples of a basic capacity, said modules being totally passive, that is they provide no signal indicative of their own capacity or presence. Each memory locations is ideally belonging to one of several memory blocks, each of capacity equal to the basic one and belonging to one of the modules.
    The addressing of a memory location involves the selection of the module containing such location by means of an auxiliary memory or directory where each addressable location is related to one of the possible memory blocks, such location being loaded with an information representative of the belonging of the related block to the pertaining module.
    Each directory location, when read, provides a suitable signal of module selection.
    The invention method solves the problem of the initial loading of the directory with the information corresponding to the real constitution of the memory and consists of the following steps:

    - writing in the directory locations of an information of belonging of the memory blocks to a hypothetical first module,
    - writing of test codes into memory locations belonging to different blocks
    - checking by reading out the content of the same memory locations if such locations belong to the first module.

    Once this checking has been performed, the above operations are repeated by writing into directory locations related to memory blocks not belonging to the first module information of belonging to a hypothetical subsequent module, by writing test codes into memory locations included in blocks not belonging to the first module and by checking the belonging of such blocks to the subsequent module, and so on for further subsequent modules up to depletion of the possible modules.

    摘要翻译： 在数据处理系统中的存储器映射方法，其中存储器包括多个模块，其容量可变为基本容量的倍数，所述模块是完全被动的，即它们不提供指示其自身容量或存在的信号。 每个存储器位置理想地属于几个存储器块中的一个，每个存储器块的容量等于基本容量，并且属于其中一个模块。 存储器位置的寻址涉及借助于辅助存储器或目录选择包含这种位置的模块，其中每个可寻址位置与可能的存储器块中的一个相关，这样的位置被加载有表示该 相关模块到相关模块。 每个目录位置在读取时提供一个合适的模块选择信号。 本发明方法解决了利用与存储器的实际构成相对应的信息初始加载目录的问题，并且包括以下步骤： - 将存储器块的所有权信息写入目录位置到假定的第一 模块， - 将测试代码写入属于不同块的存储器位置 - 如果这些位置属于第一模块，则通过读出相同存储器位置的内容来进行检查。 一旦执行了该检查，通过写入与不属于属于假设的后续模块的第一模块信息有关的存储器块的目录位置，通过将测试代码写入包含在不属于 第一个模块，并通过检查这些块到下一个模块的所属，等等，以便进一步后续的模块直到可能的模块耗尽。

    Multiprocessor system with global data replication and two levels of address translation units
    3.
    发明公开
    Multiprocessor system with global data replication and two levels of address translation units 失效
    多处理器系统的全球数据复制和地址转换单位两个层次。

    公开(公告)号：EP0387644A1

    公开(公告)日：1990-09-19

    申请号：EP90104155.8

    申请日：1990-03-03

    申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.

    发明人： Casamatta, Angelo ,  Mantellina, Calogero ,  Zanzottera, Daniele

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0284 ,  G06F12/0692 ,  G06F12/1027

    摘要： In a multiprocessor system having global data replication in each of the local memories, each associated with one of the processors, the global data allocation in the several local memories is performed by translating global data logical addresses in addresses conventionally defined as real, the translation being performed by a first translation unit associated to and managed bythe processor which generates the global data, the first translation being followed by the translation of the real address in a physical address generally differing for each local memory and performed by a plurality of translation unis, each associated with a one of the local memories and managed by the processor associated with that local memory.

    摘要翻译： 在具有在每个本地存储器全局数据复制的多处理器系统中，每个与所述处理器中的一个相关联，在几个局部存储器中的全局数据分配执行通过翻译全局数据的逻辑地址转换成常规定义为真实地址，翻译为 通过关联和bythe哪个基因利率全局数据，第一翻译由真实地址的物理地址基因的反弹不同的每个本地存储的翻译随后处理器管理和翻译学院，每一个多元化执行的第一翻译单元进行 通过与当地相关内存的处理器的本地存储器的一个相关联，并管理做到了。

    Data processing system having dual arbiter for controlling access to a system bus
    5.
    发明公开
    Data processing system having dual arbiter for controlling access to a system bus 失效
    Zenwegarbiter zur Steuerung des Zugangs zu einem Systembus的Datenverarbeitung系统。

    公开(公告)号：EP0399204A1

    公开(公告)日：1990-11-28

    申请号：EP90107202.5

    申请日：1990-04-17

    申请人： BULL HN INFORMATION SYSTEMS ITALIA S.p.A.

    发明人： Bozzetti, Fabio ,  Grassi, Maurizio ,  Mantellina, Calogero

    IPC分类号： G06F13/364

    CPC分类号： G06F13/364

    摘要： Data processing system having dual arbiter for controlling access to a system bus, where two processors, each clocked by one of two timing signals having equal period but out phases of half a period, operate synchronously each to the other, but outphased of the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor, on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.

    摘要翻译： 具有用于控制对系统总线的访问的双仲裁器的数据处理系统，其中两个处理器由两个定时信号中的一个计时，其中两个定时信号具有相同周期但是两个周期的半个周期，每个同步运行到另一个，但是在半周期 并且产生等同优先级信号，请求对系统总线的访问，每个处理器处于相应定时信号的时间不同和非重叠阶段的时间，并且其中仲裁单元授权系统总线访问任何一个或另一个请求处理器 在接收请求信号的时间顺序上，授权是异步执行的，不进行采样和建立延迟。