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151.发明公开WONDER GENERATOR, DIGITAL LINE TESTER COMPRISING THE SAME, AND PHASE NOISE TRANSFER CHARACTERISTIC ANALYZER 有权DIESEN ENTHALTENDER数字数位仪表
公开(公告)号：EP1164696A1
公开(公告)日：2001-12-19
申请号：EP00985833.3
申请日：2000-12-22
申请人： Anritsu Corporation
CPC分类号： G06F1/0335 , G06F7/584 , H04L1/24 , H04L25/03343
摘要： A wander generator has a random number signal generator unit, a filter unit, a clock generator unit, a modulator unit, and a setting unit. The random number generator unit sequentially generates random number signals comprised of a plurality of bits at a constant speed in accordance with a predetermined algorithm. The filter unit receives a random number signal sequence generated by the random number signal generator unit for filtering. The clock generator unit generates a clock signal. The modulator unit modulates the frequency of clock signal generated by the clock generator unit with a signal output from the filter unit. The setting unit applies the filter unit with a signal for setting each amplitude value of a spectrum of a signal sequence output from the filter unit.
摘要翻译： 漂移发生器具有随机数信号发生器单元，滤波器单元，时钟发生器单元，调制器单元和设置单元。 随机数发生器单元根据预定算法顺序地以恒定速度生成由多个位组成的随机数信号。 滤波器单元接收由随机数信号发生器单元产生的用于滤波的随机数信号序列。 时钟发生器单元产生时钟信号。 调制器单元利用从滤波器单元输出的信号来调制由时钟发生器单元产生的时钟信号的频率。 设置单元对滤波器单元施加用于设置从滤波器单元输出的信号序列的频谱的每个振幅值的信号。
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公开(公告)号：EP0841756A3
公开(公告)日：2001-11-28
申请号：EP97308945.1
申请日：1997-11-07
发明人： Hyyrylainen, Jari , Ylamurto, Tommi
CPC分类号： H04B1/30 , H03D3/007 , H03H7/21 , H03H2007/0192
摘要： A correlator circuit for a six port receiver wherein the received signal is summed with a local oscillator signal at various phase angles and wherein the phase rotation between the local oscillator and RF signals is carried out separately from the summing of the correlator outputs.
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公开(公告)号：EP1047946A1
公开(公告)日：2000-11-02
申请号：EP98964801.9
申请日：1998-12-17
申请人： INTEL CORPORATION
发明人： JOHNSON, Luke, A.
IPC分类号： G01R25/00
摘要： A self-compensating phase detector using two identical phase detectors (21, 22) introducing one of the phase detectors and a control variable phase shifter (20) in a negative feedback loop (23) shifts one clock signal enough such that shifted signal compensates for existing static phase error. This self-compensation improves the accuracy of the phase difference measurement by significantly reducing the effect of the static phase error. Moreover, this reduction remains true in spite of variations in process, temperature and voltage. Thus, inherent immunity of the invention to environmental conditions results in fewer failing parts during fabrication. Additionally, because the design is self-adjusting to environmental changes, design ease is significantly improved.
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154.发明公开Pulse-width based phase detector having a extended output range 审中-公开Pulsbreitenmodulierter Phasendetektor mit erweitertem Ausgangsbereich
公开(公告)号：EP0926813A1
公开(公告)日：1999-06-30
申请号：EP98118668.7
申请日：1998-10-02
CPC分类号： G01R25/00 , H03D13/004 , H03L7/081 , H03L7/089
摘要： A circuit[20] for generating a signal that is proportional to the phase difference between a reference signal and a variable frequency signal. The circuit[20] includes a reference generating circuit[21] for generating N phase shifted reference signals from the reference signal. Each of the phase shifted reference signals has the same frequency and a different phase. The phase of the n th one of the phase shifted reference signals is equal to 360n/N degrees, where N>1 and n runs from 0 to N-1. A phase detection circuit[22] generates a phase output signal proportional to the phase difference between the variable frequency signal and the phase shifted reference signal currently being outputted by the reference generating circuit. The phase output signal has value of I when the output signal corresponds to a phase difference of 360/N degrees. An overflow detection circuit[24] determines when the phase output signal has an absolute value greater than I and generates a count signal and a phase adjustment signal when this situation is detected. The phase adjustment signal is coupled to the reference generating circuit[21] and causes the reference generating circuit[21] to select a new phase shifted reference signal. A counter[25] is then incremented/decremented to track the accumulated phase adjustments. A digital to analog converter[26] converts the digital value in the counter[25] to a signal having an amplitude equal to MI, where M is the digital value. A sum circuit[27] adds this signal to the phase output signal.
摘要翻译： 用于产生与参考信号和可变频率信号之间的相位差成比例的信号的电路。 电路包括用于从参考信号产生N个相移参考信号的参考产生电路。 每个相移参考信号具有相同的频率和不同的相位。 相移参考信号中的第n个相位等于360n / N度，其中N≥1且n从0到N-1。 相位检测电路223产生与参考发生电路当前正在输出的可变频率信号和相移参考信号之间的相位差成比例的相位输出信号。 当输出信号对应于360 / N度的相位差时，相位输出信号的值为I。 当检测到这种情况时，溢出检测电路确定相输出信号何时具有大于I的绝对值，并产生计数信号和相位调整信号。 相位调整信号耦合到参考产生电路Ä21Ü，使参考产生电路Ä21 to选择新的相移基准信号。 然后递增/递减counterÄ25Ü以跟踪累积的相位调整。 数模转换器266将转换器中的数字值转换成幅度等于MI的信号，其中M是数字值。 总和电路将这个信号加到相位输出信号上。
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155.发明授权Frequency divider, frequency measurement circuit and pulse generator using a common delay circuit 失效频率测量和脉冲发生器与一个共同的延迟电路分频电路
公开(公告)号：EP0660518B1
公开(公告)日：1999-06-09
申请号：EP94120564.3
申请日：1994-12-23
申请人： DENSO CORPORATION
CPC分类号： H03K3/0315 , H03K5/135
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公开(公告)号：EP0613015B1
公开(公告)日：1999-01-20
申请号：EP94107920.4
申请日：1989-09-25
CPC分类号： G01R13/345 , G01R15/247
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公开(公告)号：EP0889411A2
公开(公告)日：1999-01-07
申请号：EP98305134.3
申请日：1998-06-29
发明人： Smith, Larry D. , ABT, Norman E.
摘要： An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1Δt. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2)Δt. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized. The digitized output signal identifies the lowest duty cycle two-input logic element, and thus phase shift. The relative breadth of the integrated capacitor voltage profile provides a measure of average maximum jitter.
摘要翻译： 一个ASIC包括PLL电路和数字电路来量化和测量系统时钟输入到PLL一个，和一个PLL的生成的时钟信号之间的相位和平均最大抖动。 该系统时钟被输入到延迟元件的串联串，每个贡献约1 DELTA吨的延迟。 每个门延迟元件与一个两输入逻辑元件相关联，：诸如EX-OR门或EX-NOR。 一个输入到每两个输入逻辑元件是由大约（N / 2）DELTA吨延迟PLL产生的时钟的一个版本。 第二输入与第一EX-OR是来自第一延迟元件的输出，第二输入到第一EX-NOR是来自第二延迟元件的输出，等等。 无论延迟元件与所述延迟PLL生成的时钟必须与最小工作循环相关联的两个输入逻辑元件的信号相位关系最密切输出信号。 每两个输入逻辑元件输出信号进行积分电容器，采样，存储和数字化。 数字化输出信号标识的最低占空比双输入逻辑元件，因此相移。 该整合电容器的电压分布的相对宽度提供平均最大抖动的测量。
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158.发明公开
公开(公告)号：EP0793109A4
公开(公告)日：1998-03-11
申请号：EP95937750
申请日：1995-11-17
发明人： HAO YUSHAN
CPC分类号： G01R25/00
摘要： The present invention relates to a measuring method and a system of phase angle of electrical system sinusoidal quantities, the method includes selecting a key station as a reference station, other stations desired to be measured as sub-stations in electrical system, establishing an unitized standard unit of time, and so, avoids delay in signal transference. Further, signals which are designated with standard unit of time are compared to each other, in order to find the phase angle of the signals. Otherwise, the signal of the reference station may also be transferred to the sub-stations as a reference signal. The signals which are transferred to the sub-stations are corrected and compensated for phase delay in transference, further they and the measured signals of the sub-stations are calculated in order to find the phase angle. Since the present method is used to measure the phase angles of electrical system sinusoidal quantities, the electrical system can be measured in real time, therefore the method provides a new way to measure phase angle easily.
摘要翻译： 本发明涉及一种测量方法和电气系统的正弦量的相位角的系统，该方法包括选择一个关键电台作为参考站，希望的其它站将被测量为在电气系统分站，建立单元化标准的 的时间单位，因此避免了在信号传递的延迟。 此外，被指定为时间标准单位信号，以便找到该信号的相位角相比海誓山盟。 否则，该基准站的信号可以因此被转移到分站作为参考信号。 哪个被传输到子站的信号进行校正，并在转移的相位延迟得到补偿，此外，它们与分站的测量的信号，以便找到的相位角进行计算。 由于重新发送的方法被用于测量电气系统正弦量的相位角，电气系统可以实时测量，因此，该方法提供了容易地测量相位角的新方法。
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公开(公告)号：EP0787304A1
公开(公告)日：1997-08-06
申请号：EP95935716.0
申请日：1995-10-12
发明人： CALERO, Fernando
CPC分类号： G01R19/0038 , G01R19/25 , G01R19/2513 , G01R21/133 , G01R25/00 , G01R31/02 , H02H3/003 , H02H3/38 , H02H3/382 , H02H3/385 , H02H3/402
摘要： A numerical comparator (20) is disclosed. The numerical comparator (20) employs numerical techniques based upon the behavior of the cylinder unit (18) to compare phasors in real time. In one application of this invention, the torque signal generated by the numerical comparator, Mk+1, is employed to determine whether a fault has occurred in a transmission line. Another application involves employing the output Mk+1 to determine the direction of power flow in the transmission line. In yet another application, the output Mk+1 is used to determine whether a voltage or current has exceeded a predetermined threshold.
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公开(公告)号：EP0715723A4
公开(公告)日：1997-04-23
申请号：EP94924527
申请日：1994-08-02
申请人： ECHELON CORP
发明人： NAJAM ZAHID
摘要： A transmitting box (101) is connected to a first electrical outlet in a building. The phase of the first electrical outlet is used as the reference phase. The transmitter box senses each of the zero-cross-overs of the reference phase and injects a data packet of the data carrier frequency at each zero-cross-over. A receiving box (103) is connected to a second electrical outlet in the building. The second electrical outlet has a test phase which may be different from the reference phase. The receiver box receives each data packet and senses each phase zero-cross-over of the test phase. The receiver box uses the time between each reception of a data packet and each detection of a test phase zero-cross-over to determine the phase angle of the test phase relative to the reference phase.
摘要翻译： 发射箱连接到建筑物中的第一电插座。 第一个电源插座的相位用作参考相位。 发射机盒感应参考相位的零交叉，并在每个零交叉处注入数据载波频率的数据分组。 接收盒连接到建筑物中的第二电源插座。 第二电源插座具有与参考相位不同的未知相位。 接收器盒接收每个数据包并且感测未知相位的每个相位零交叉。 接收机盒使用每次接收数据包和每次检测未知相位零交叉之间的时间来确定未知相相对于参考相位的相位角。
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