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    THREE PHASE FREQUENCY SENSOR WITH OPEN/SHORT IMMUNITY
    1.
    发明公开
    THREE PHASE FREQUENCY SENSOR WITH OPEN/SHORT IMMUNITY 审中-公开

    公开(公告)号：EP4431952A1

    公开(公告)日：2024-09-18

    申请号：EP24163481.5

    申请日：2024-03-14

    申请人： Hamilton Sundstrand Corporation

    发明人： BLAZER, Christopher

    IPC分类号： G01R23/02 ,  G01R25/00

    CPC分类号： G01R23/02 ,  G01R25/005

    摘要： A frequency sensor system for a three-phase generator includes a first stage (302) that receives all three phases of the three-phase generator and generates three scaled difference signals from them. The system also includes a summing and filtering stage, the summing and filtering stage combining the three scaled difference signals to form a single combined signal and the filtering the single combined signal with an active filter to produce a filtered combined signal. The system also includes a gain stage (360) that amplifies the filtered combined signal to form an amplified filtered combined signal and a comparator (650) that converts the amplified filtered combined signal into a digital output having a frequency that matches a frequency of the amplified filtered combined signal.

    SYSTEM FOR MEASURING PERFORMANCE OF EQUIPMENT UNDER TEST, AND METHOD THEREFOR
    3.
    发明公开
    SYSTEM FOR MEASURING PERFORMANCE OF EQUIPMENT UNDER TEST, AND METHOD THEREFOR 审中-实审

    公开(公告)号：EP4390410A1

    公开(公告)日：2024-06-26

    申请号：EP21964903.5

    申请日：2021-12-07

    申请人： National Radio Research Agency

    发明人： KIM, Kang Wook ,  OH, Soon Soo ,  JUNG, Young Bae ,  LIM, Jong Hyuk

    IPC分类号： G01R29/08 ,  G01R29/10 ,  G01R1/073 ,  G01R25/00

    CPC分类号： G01R29/10 ,  G01R1/073 ,  G01R25/00 ,  G01R29/08

    摘要： Disclosed are a system and a method therefor, the system enabling high-speed measurement of the performance of a plurality of measurement items for verification and post management of equipment under test including an antenna under test. According to one aspect of the present invention, provided is a system for measuring the performance of equipment under test, comprising: a fixing part for fixing the equipment under test, which is to be tested; a positioner for controlling the rotation of the equipment under test by controlling the fixing part; a measurement probe, which is provided at a predetermined position spaced apart from the fixing part while being hidden from the line-of-sight of the equipment under test; a curved reflective plate for reflecting, in the direction of the measurement probe, an electromagnetic wave radiated by the equipment under test and transforming the spherical wave of the measurement probe into a plane wave at the position where the equipment under test is provided; an arc structure including an arc arranged to be adjacent to the fixing part so that the position of the equipment under test is the center point of the arc; a probe set including a plurality of near-filed probes arranged to be spaced predetermined intervals apart from each other on the inner side of the arc; and a control unit, which receives, through a signal analyzer, signal data corresponding to an input signal from at least some of the plurality of near-filed probes and the measurement probe in order to measure the performance of the equipment under test.

    DETECTION DE SIGNAUX I ET Q
    4.
    发明公开
    DETECTION DE SIGNAUX I ET Q 审中-实审

    公开(公告)号：EP4361648A1

    公开(公告)日：2024-05-01

    申请号：EP23203527.9

    申请日：2023-10-13

    申请人： STMicroelectronics France

    发明人： GIRY-CASSAN, Florence

    IPC分类号： G01R25/00 ,  H03B27/00 ,  H04L27/34

    CPC分类号： H04L27/34 ,  H03B27/00 ,  G01R25/005

    摘要： La présente description concerne un dispositif comprenant un circuit recevant deux signaux sinusoïdaux (sig1, sig3) en quadrature et fournissant :
    - un premier signal carré (sig11) correspondant à un premier des deux signaux, et
    - un deuxième signal carré (sig31) correspondant à un deuxième des deux signaux ; et
    une porte logique recevant les deux signaux carrés (sig11, sig31) et fournissant, quand les premier et deuxième signaux carrés sont simultanément à un premier niveau, des troisième et quatrième signaux carrés (O1, O2) respectivement à un premier niveau et à un deuxième niveau si le premier signal sinusoïdal est en avance de phase, et respectivement au deuxième niveau et au premier niveau si le deuxième signal sinusoïdal est en avance de phase.

    ELECTRONIC CIRCUITRY, SYSTEM, BASE STATION, MOBILE DEVICE AND METHOD
    5.
    发明公开
    ELECTRONIC CIRCUITRY, SYSTEM, BASE STATION, MOBILE DEVICE AND METHOD 审中-公开

    公开(公告)号：EP4345467A1

    公开(公告)日：2024-04-03

    申请号：EP22198582.3

    申请日：2022-09-29

    申请人： INTEL Corporation

    发明人： BEN-BASSAT, Assaf ,  BOROKHOVICH, Eli ,  SKLIAR, Phillip

    IPC分类号： G01R21/06 ,  G01R25/08 ,  G01R27/28

    摘要： An electronic circuitry is proposed. The electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. The electronic circuitry further comprises a Time-to-Digital converter, TDC, coupled to the third port and the fourth port. The TDC is configured to determine a phase difference between the forward signal and the reverse signal.

    AUTOMATIC POWER FACTOR CORRECTION
    9.
    发明公开
    AUTOMATIC POWER FACTOR CORRECTION 审中-公开

    公开(公告)号：EP4187763A1

    公开(公告)日：2023-05-31

    申请号：EP22209403.9

    申请日：2022-11-24

    申请人： Hamilton Sundstrand Corporation

    发明人： WINER, Gordon Elliott

    IPC分类号： H02M1/00 ,  H02M1/42 ,  H02J3/18 ,  G01R25/00

    摘要： Systems for power factor correction are provided. Aspects include a voltage source connected to a first node, wherein the voltage source is configured to provide a first voltage, a sense resistor connected between the first node and a second node, a load connected to the second node, a power factor correction capacitor (222, 422, 522) connected in parallel with the load, and a controlled voltage source configured to provide a second voltage to the power factor correction capacitor (222, 422, 522) based on a control signal, wherein the control signal is received from a power factor correction circuit configured to determine a time difference between a zero-crossing of a voltage signal and a zero-crossing of a current signal from the voltage source.