摘要:
A method for controlling memory components of 16K x 1 bit or 64K x 1 bit by employing a control bus adapted to components of 4K x 1 bit, wherein a memory refresh signal (REF) is generated indpendent of the one supplied by the system. A memory circuit board, particularly, but not exclusively, a memory circuit board for a system for inspecting or testing electronic components, having a capacity of 32K or 64K words of 24 data bits and one parity bit, and including a refresh signal generating block (REFRESH TIMING) operating according to the method defined above.
摘要翻译:产生独立于一个由系统提供的,用于通过使用控制总线angepasst至4K X 1位组件,worin存储器刷新信号(REF)控制的16K X 1比特或64K X 1位存储器元件的方法,一种 存储器电路板,特别是,但不是排他地,对于用于检查或测试电子部件,其具有的容量为32K或24个数据位和一个奇偶校验位64K字,并且包括刷新信号生成块的系统的存储器电路板(REFRESH 定时)操作gemäß上面定义的方法。
摘要:
Household appliance (1) comprising a control device (5) and a transmitter (2), as well as a receiver (3) which is located remote therefrom in correspondence of whatever points of the supply mains (14) and is capable of operating a warning device (10). In case the appliance does not operate correctly the control device (5) is capable of generating an alarm signal which causes transmitter (2) to send via the supply mains (14) a control signal to the receiver (3) which then operates the warning device (10) accordingly.
摘要:
Described is an automatic machine for washing articles in a bath containing surfactant substances. The machine is provided with a device for detecting microscopic characteristics of micelles and emulsion in the washing bath and for generating signals corresponding to such characteristics for controlling programmable means for the control of operative components of the machine.
摘要:
An actuator (3) is adapted to be controlled for deenergizing the direction indicators by the output of a comparator (4) having a first input(5) supplied with a reference value through a potentiometer (7) operatively connected to the steering wheel of the vehicle. A second input (6) of the comparator (4) is connected to said reference voltage potentiometer through a peak value memory stage (10) and a peak value divider stage (11) connected in series with said potentiometer (7). The memory stage (10) has a reset input (13) controlled by the output of the comparator.