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454 条记录 (耗时 0.027 秒)

    TESTING A FEEDBACK SHIFT-REGISTER
    1.
    发明公开
    TESTING A FEEDBACK SHIFT-REGISTER 有权
    导读反馈移位寄存器

    公开(公告)号：EP3105674A1

    公开(公告)日：2016-12-21

    申请号：EP13817757.1

    申请日：2013-11-28

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： SELANDER, Göran ,  NÄSLUND, Mats ,  DUBROVA, Elena

    IPC分类号： G06F7/58 ,  G01R31/3181 ,  G11C19/00

    CPC分类号： G01R31/31703 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/31813 ,  G01R31/318547 ,  G11C19/28 ,  G11C29/02 ,  G11C29/021

    摘要： A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.

    DETECTION OF BROKEN WORD-LINES IN MEMORY ARRAYS
    4.
    发明公开
    DETECTION OF BROKEN WORD-LINES IN MEMORY ARRAYS 有权
    检测半导体存储器阵列断字线

    公开(公告)号：EP2591472A1

    公开(公告)日：2013-05-15

    申请号：EP11729863.8

    申请日：2011-06-24

    申请人： SanDisk Technologies Inc.

    发明人： SHAH, Grishma Shailesh ,  LI, Yan

    IPC分类号： G11C29/02

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/702 ,  G11C2029/1202

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

    ADJUSTING A DIGITAL DELAY FUNCTION OF A DATA MEMORY UNIT
    6.
    发明授权
    ADJUSTING A DIGITAL DELAY FUNCTION OF A DATA MEMORY UNIT 有权
    调整数字延迟功能的数据存储单元的

    公开(公告)号：EP1997112B1

    公开(公告)日：2011-03-02

    申请号：EP06725144.7

    申请日：2006-03-17

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： RUTHEMANN, Klaus

    IPC分类号： G11C29/02 ,  G11C7/10 ,  G11C8/06

    CPC分类号： G11C7/1036 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C29/003 ,  G11C29/02

    摘要： An apparatus for adjustment of a digital delay function of a data memory unit comprising said data memory unit (102), an elastic store register, ESR, (104) and read clock and write clock adapted to control read and write operations, a write counter associated with the write clock and a read counter associated with the read clock. Said memory (102) works in series with said ESR (104). The memory (102) delivers two data elements from two logically neighbouring cells. Said ESR (104) writes the two data elements from the memory (102) at every cycle of the write clock, wherein if the write counter is increased by one at a cycle of the write clock the output position in the memory (102) is not changed, and if the write counter is increased by two at one cycle of the write clock the output position in the memory (102) is moved backward by one data element and if the write counter is not changed at one cycle of the write clock the output position in the memory (102) is moved forward by one data element.

    Device and method for compensating for voltage drops
    9.
    发明公开
    Device and method for compensating for voltage drops 审中-公开
    Vorrichtung und Verfahren zum Ausgleichen vonSpannungsabfällen

    公开(公告)号：EP2226641A2

    公开(公告)日：2010-09-08

    申请号：EP09171681.1

    申请日：2005-07-05

    申请人： Freescale Semiconductor, Inc.

    发明人： Sofer, Sergey ,  Fefer, Yefim - Haim ,  Neiman, Valery

    IPC分类号： G01R31/28 ,  G05F1/56

    CPC分类号： G11C29/02 ,  G05F1/56 ,  G11C5/025 ,  G11C5/147 ,  G11C29/021 ,  G11C29/028

    摘要： A method (100) for power supply voltage drop compensation within the integrated circuit. The method (100) comprises providing (105) a supply voltage to an integrated circuit.
    The method (100) comprises:
    sampling (110) voltage levels at multiple sampling points within the integrated circuit, to provide multiple sampled voltages, wherein the multiple sampled voltages reflect the voltage drops at the multiple sampling points; and
    adjusting (170) a voltage supply provided to the integrated circuit in response to at least one sampled voltage; wherein the providing (105) comprises providing a supply voltage that substantially compensates for the response period.

    摘要翻译： 一种用于集成电路内的电源电压降补偿的方法（100）。 方法（100）包括向集成电路提供（105）电源电压。 所述方法（100）包括：在所述集成电路内的多个采样点处采样（110）电压电平，以提供多个采样电压，其中所述多个采样电压反映所述多个采样点处的电压降; 以及响应于至少一个采样电压来调整（170）提供给所述集成电路的电压源; 其中所述提供（105）包括提供基本上补偿所述响应周期的电源电压。