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公开(公告)号：EP0579875A1
公开(公告)日：1994-01-26
申请号：EP92202292.6
申请日：1992-07-24
IPC分类号： H03H11/04
CPC分类号： H03H11/0472 , H03H11/0433
摘要： Based on the insight that the damping of a tunable filter is both related to its quality factor as to its passband gain, an inventive tuning system is proposed which tunes the quality factor of such a filter to a desired quality factor value by tuning the passband gain of the filter to a desired gain value.
Such a tuning system is particularly useful in the field of OTA-C filters and consists of first (P1) and second (P2) tuning paths including such a tunable filter (BIQUAD) and fixed gain amplifiers (B-OTA1, B-OTA2). The gain of the latter amplifiers corresponds to the desired gain values. The tuning system further includes matching means (MM) for equalizing the gains in both tuning paths (P1, P2) by generating a quality factor tuning signal (VTQ) which is applied both to the tunable filter (BIQUAD) and to a replica thereof used as master filter in a data processing path.
This matching means (MM) includes current rectifiers (C-REC1, C-REC2) implemented so as to use little hardware.摘要翻译： 基于对可调谐滤波器的阻尼与其通带增益的质量因子有关的认识，提出了一种本发明的调谐系统，其通过调谐通带增益来调节这种滤波器的品质因数至期望的品质因数值 的滤波器到期望的增益值。 这样的调谐系统在OTA-C滤波器领域中特别有用，并且由包括这种可调滤波器（BIQUAD）和固定增益放大器（B-OTA1，B-OTA2）的第一（P1）和第二（P2）调谐路径组成， 。 后一放大器的增益对应于期望的增益值。 调谐系统还包括用于通过生成适用于可调谐滤波器（BIQUAD）和其所使用的副本的质量因子调谐信号（VTQ）来均衡两个调谐路径（P1，P2）中的增益的匹配装置（MM） 作为数据处理路径中的主过滤器。 该匹配装置（MM）包括实现为使用少量硬件的电流整流器（C-REC1，C-REC2）。
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12.发明公开Data transfer apparatus comprising a primary device connected to a plurality of secondary devices 失效主设备和用线的数量有限的多个次级装置之间的数据传输连接。
公开(公告)号：EP0461309A1
公开(公告)日：1991-12-18
申请号：EP90201197.2
申请日：1990-05-11
IPC分类号： H04L12/403
CPC分类号： H04L12/4135 , H04L12/40
摘要： The primary device (DSP) is connected to m x n secondary devices (ESLIC1-4) by one data link (IOB) comprising the m x n data channels assigned to respective secondary devices (ESLIC1-4) say m clock links (GKC0-1) connected to m respective groups each of n secondary devices (ESLIC1-3; ESLIC2-4) and carrying m clock signals having a same clock frequency and being mutually shifted by 1/m th of a cycle of the clock frequency, and by n read/write links (RD0-1) connected to n respective groups each of m secondary devices (ESLIC1-2; ESLIC3-4) and carrying n read/write signals mutually shifted by one cycle of the clock frequency, each secondary device (ESLIC1-4) belonging to a distinct pair of one group out of the m groups (ESLIC1-3; ESLIC2-4) and of one group out of the n groups (ESLIC1-2; ESLIC3-4).
摘要翻译： 主设备（DSP）连接通过一个数据链路（IOB）包括分配给respectivement次级装置（ESLIC1-4）连接到所述m×n个数据信道说米时钟链路（GKC0-1）至MXN辅助设备（ESLIC1-4） 米respectivement组每个n次级装置（ESLIC1-3; ESLIC2-4）和携带具有相同的时钟频率和由1 / M被相互偏移m个时钟信号
时钟频率的周期的，和由n个读 /左写（RD0-1），其连接到n respectivement基团各为m次级装置（ESLIC1-2; ESLIC3-4）和携带n读取由时钟频率，每个次级装置的一个周期相互偏移/写信号（ESLIC1- 4）属于不同对中的一个组的出m个组（ESLIC1-3的; ESLIC2-4）和一组出n个组（ESLIC1-2的; ESLIC3-4）。 -
公开(公告)号：EP0476215B1
公开(公告)日：1995-12-13
申请号：EP90870154.3
申请日：1990-09-18
IPC分类号： H03H17/06
CPC分类号： H03H17/0607 , H03H17/0621 , H03H17/0664 , H03H2218/06
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公开(公告)号：EP0476215A1
公开(公告)日：1992-03-25
申请号：EP90870154.3
申请日：1990-09-18
IPC分类号： H03H17/06
CPC分类号： H03H17/0607 , H03H17/0621 , H03H17/0664 , H03H2218/06
摘要： 5n7 A multi-sample multi-channel decimator producing a FIR filtering response from 128 digital filter coefficients for 4 independent channels with a decimation ratio of 32, i.e. from 1 MHz 1-bit inputs to 32 kHz multibit outputs, splits cyclically the coefficient values in 16 groups of 8, according to the coefficient positions, into 4 ROMs (0, 1, 2, 3). The ROMs are coupled to the 4 multipliers (MULT 0, 1, 2, 3), wherein the coefficient value is multiplied by that of the input bit, through a multiplexer (MUXI) able to cycle through 4 distinct conditions. After the 4 adder accumulators (ACC 0, 1, 2, 3) coupled to the outputs of their respective channel multipliers have, in parallel partially computed output words, each using one sixteenth of the coefficients, the multiplexer rotates these, thereby enabling complete computation in 4 cycles, 4 registers (REG 00, 01, 02, 03) being associated to each adder so as to compute 4 staggered output words simultaneously for each channel. A preferred filtering response can reduce the size of the ROMs.
摘要翻译： 一个多采样多通道抽取器产生一个来自128个数字滤波器系数的FIR滤波响应，用于4个独立通道，抽取比为32，即从1MHz 1位输入到32 kHz多位输出，循环分解16组中的系数值 的8个，根据系数位置，分为4个ROM（0，1，2，3）。 这些ROM耦合到4个乘法器（MULT 0,1,2,3），其中系数值乘以输入位的系数值，通过能够循环通过4个不同条件的多路复用器（MUXI）。 在耦合到其各自的信道乘法器的输出的4个加法器累加器（ACC 0，1，2，3）之后，在并行部分计算的输出字中，每个使用十六分之一系数，多路复用器旋转它们，从而使得能够完全计算 在4个周期中，4个寄存器（REG 00,01,02,03）与每个加法器相关联，以便为每个通道同时计算4个交错的输出字。 优选的过滤响应可以减小ROM的大小。
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15.发明授权Data transfer apparatus comprising a primary device connected to a plurality of secondary devices 失效一种数据传输设备，包括连接到多个次级装置的一个主装置。
公开(公告)号：EP0461309B1
公开(公告)日：1995-08-23
申请号：EP90201197.2
申请日：1990-05-11
IPC分类号： H04L12/403
CPC分类号： H04L12/4135 , H04L12/40
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16.发明公开
公开(公告)号：EP0579876A1
公开(公告)日：1994-01-26
申请号：EP92202293.4
申请日：1992-07-24
IPC分类号： H03H11/04
CPC分类号： H03H11/0472 , H03H11/0433
摘要： Based on the insight that the voltage-to-current ratio or gain of a capacitor (Z) at a particular reference frequency is the product of its capacitance value with said reference frequency, a tuning system is disclosed which tunes the characteristic integrator frequency (fc) of an OTA-C integrator by making the transconductance of the operational transconductance amplifier (OTA) thereof equal to the aforementioned gain at that characteristic frequency. Therefore, the tuning system includes a first tuning path in which the OTA (or a replica thereof) is included and a second tuning path including another amplifier (B-OTA) "degenerated" by the capacitor (Z) so as to produce the required gain. The gains of both these tuning paths are then equalized by matching means (MM) generating a frequency tuning signal (VTF) which is applied to both OTA and OTA-C.
摘要翻译： 基于以下认识：特定参考频率下的电容器（Z）的电压 - 电流比或增益是其电容值与所述参考频率的乘积，公开了调谐特性积分器频率（fc ）的OTA-C积分器通过使其运算跨导放大器（OTA）的跨导等于在该特征频率处的上述增益。 因此，调谐系统包括其中包括OTA（或其复制品）的第一调谐路径和包括由电容器（Z）“退化”的另一个放大器（B-OTA）的第二调谐路径，以便产生所需的 获得。 然后通过产生施加于OTA和OTA-C两者的频率调谐信号（VTF）的匹配装置（MM）来均衡两个这些调谐路径的增益。
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公开(公告)号：EP0483125A3
公开(公告)日：1992-12-23
申请号：EP92200259.7
申请日：1988-06-30
CPC分类号： G05F3/242 , H03K3/35613 , H03K3/356191
摘要： The subject of the present invention is a current source (BS) which is associated to a bistate device (ST), a bistable device (FF) and an input circuit (IC) for constituting a signal comparator. The current source (BS) uses a current mirror configuration and is controlled via a branch coupled between the voltage supply terminals (VDD; VSS), two (N2, N3) of the four (N1 to N4) series connected transistors forming part of this branch have a relatively great Width-by-Length W/L channel parameter so that identical current sources (BS) may be produced on a large scale because the current (I5; II) supplied by the latter is then independent of the threshold voltages of the constituent transistors.
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公开(公告)号：EP0483125A2
公开(公告)日：1992-04-29
申请号：EP92200259.7
申请日：1988-06-30
CPC分类号： G05F3/242 , H03K3/35613 , H03K3/356191
摘要： The subject of the present invention is a current source (BS) which is associated to a bistate device (ST), a bistable device (FF) and an input circuit (IC) for constituting a signal comparator. The current source (BS) uses a current mirror configuration and is controlled via a branch coupled between the voltage supply terminals (VDD; VSS), two (N2, N3) of the four (N1 to N4) series connected transistors forming part of this branch have a relatively great Width-by-Length W/L channel parameter so that identical current sources (BS) may be produced on a large scale because the current (I5; II) supplied by the latter is then independent of the threshold voltages of the constituent transistors.
摘要翻译： 本发明的主题是与用于构成信号比较器的双稳态器件（ST），双稳态器件（FF）和输入电路（IC）相关联的电流源（BS）。 电流源（BS）使用电流反射镜配置并且经由耦合在电压供应端子（VDD; VSS）之间的分支，四个（N1到N4）串联连接的晶体管中的两个（N2，N3）形成该部分的 分支具有相对较大的宽长W / L通道参数，因此可以大规模地产生相同的电流源（BS），因为后者提供的电流（I5; II）于是独立于阈值电压 组成晶体管。
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