公开(公告)号：EP0596658A1

公开(公告)日：1994-05-11

申请号：EP93308621.7

申请日：1993-10-28

申请人： AT&T Corp.

发明人： Britton, Barry Kevin ,  Hill, Dwight Douglas ,  Oswald, William Anthony

IPC分类号： H03K19/00 ,  H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/17704 ,  H03K19/1774

摘要： Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad (eg., 238 - 241; 246 - 249) may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs) (eg., 205 - 213). This is accomplished by using a criss-crossed grid of parallel conductor groups (eg., 254, 255). Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor. In this manner, each cell (eg., 201 - 204) may drive a subset of the conductors in a group, thereby reducing the number of drivers needed. This allows all the buffer and conductor topologies to be identical for each cell, which significantly aids in the computer-aided design of the FPGA, as well as simplifying its programming.

摘要翻译： 将低偏移时钟信号提供给现场可编程门阵列（FPGA）芯片通常需要为此目的投入一定数量的焊盘。 然而，这限制了可能应用的时钟数量，并且还可以限制可以为此目的使用哪些bondpads。 在本发明中，可以使用任何输入/输出接合板（例如，238-241; 246-249）来向一个或多个可编程功能单元（PFU）提供低偏移时钟或其他全局类型信号 ）（例如，205-213）。 这通过使用并联导体组的交叉格栅（例如，254,255）来实现。 任何导体可以由来自键合板的时钟提供，或者可以直接从PFU驱动，从而允许分配内部生成的时钟。 为了促进水平和垂直导体之间的可编程互连，组中的外部导体以限定的间隔跨越其它导体，从​​而变成内部导体。 以这种方式，每个单元（例如，201-204）可以驱动组中的导体的子集，从而减少所需的驱动器的数量。 这允许每个单元的所有缓冲器和导体拓扑结构相同，这有助于FPGA的计算机辅助设计，并简化其编程。