公开(公告)号：EP3261001A1

公开(公告)日：2017-12-27

申请号：EP17171944.6

申请日：2017-05-19

申请人： Altera Corporation

发明人： Langhammer, Martin

IPC分类号： G06F17/50

CPC分类号： H03K19/17704 ,  G06F15/82 ,  G06F17/50 ,  G06F17/5045 ,  G06F17/5054

摘要： A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.

摘要翻译： 可编程集成电路可以包括用于实现精简指令集计算（RISC）处理器的软逻辑和硬逻辑。 专用计算设备上实现的处理器生成器工具可用于指定处理器体系结构的所需参数，包括一个或多个数据路径的数据字大小，指令字大小和一组指令格式。 处理器生成器工具也可用于确定每个数据路径所需的适当的流水线量以满足性能标准。 处理器生成器工具也可用于分析处理器体系结构并提供缓解潜在结构和数据危害的选项。

公开(公告)号：EP2979363B1

公开(公告)日：2017-10-04

申请号：EP14718668.8

申请日：2014-03-25

申请人： Nanoxplore

发明人： LEPAPE, Olivier

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1776

公开(公告)号：EP2979363A2

公开(公告)日：2016-02-03

申请号：EP14718668.8

申请日：2014-03-25

申请人： Nanoxplore

发明人： LEPAPE, Olivier

IPC分类号： H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/1776

摘要： The invention relates to a programmable interconnection device (8) comprising: first rows (RFl, RF2) of functional blocks (Fi-F14), each functional block comprising inputs and outputs; second rows (RM1, RM2, RM3) of programmable interconnection cells (Mi-Mi4); horizontal connections (H), each of them linking a programmable interconnection cell (M8) of the second row (RM1, RM2, RM3) with just one other cell (M3; M13) of this row; and connection harnesses comprising transverse connections (B) linking one and the same programmable interconnection cell (M8) with functional blocks (F6-Fi0) of the first neighbour row (RFl, RF2); the set of cells (M1-M14) being able to interconnect between them the inputs and outputs of each functional block (Fi-Fi4) of each first row (RFl, RF2)with the outputs and the inputs of all the other functional blocks of the first row.

摘要翻译： 本发明涉及一种可编程互连设备，包括：第一行功能块，每个功能块具有输入和输出; 第二排可编程互连电池; 水平连接，每个连接第二行的可编程互连单元与该行的仅一个其他单元; 以及连接束，其包括将给定可编程互连单元与相邻第一行的功能块连接的横向连接; 这些单元适合于一起，用于将每个第一行的每个功能块的输入和输出与同一行的所有其他功能块的输出和输入相互连接。

公开(公告)号：EP2489127A4

公开(公告)日：2015-12-23

申请号：EP10824014

申请日：2010-10-13

申请人： CHAOLOGIX INC

发明人： MYERS BRENT A ,  FOX JAMES G

IPC分类号： H03K19/173 ,  G06F21/55 ,  H03K19/00 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/20 ,  H04L9/00

CPC分类号： H03K19/17768 ,  G06F21/755 ,  H01L2924/0002 ,  H03K19/0013 ,  H03K19/0944 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/20 ,  H04L9/001 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12 ,  H01L2924/00

公开(公告)号：EP1154435B1

公开(公告)日：2015-08-26

申请号：EP01120245.4

申请日：1996-02-09

申请人： Xilinx, Inc.

发明人： Freidin, Philip M. ,  Cheung, Edmond Y. ,  Erikson, Charles R. ,  Syu, Tsung-Lu

IPC分类号： G11C7/10

CPC分类号： H03K19/1736 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  H03K19/17704

公开(公告)号：EP2597777A3

公开(公告)日：2014-08-20

申请号：EP13156242.3

申请日：2007-05-27

申请人： Tabula, Inc.

发明人： Teig, Steven ,  Schmit, Herman ,  Huang, Randy, Renfu

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了包括具有存储元件的可配置路由结构的可配置IC。 在一些实施例中，路由结构提供将信号路由至源组件和目标组件的通信路径。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源组件或目的组件连续执行操作（例如，计算或路由），而不管来自或去往这种组件的先前信号是否存储在路由结构中。 源和目标组件包括可配置的逻辑电路，可配置的互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：EP2597776A2

公开(公告)日：2013-05-29

申请号：EP13156236.5

申请日：2007-05-27

申请人： Tabula, Inc.

发明人： Teig, Steven ,  Schmit, Herman ,  Huang, Randy, Renfu

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了包括具有存储元件的可配置路由结构的可配置IC。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续执行操作（例如，计算或路由），而不管来自或来自这种组件的先前信号是否存储在路由结构中。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：EP2132874B1

公开(公告)日：2010-12-01

申请号：EP08730109.9

申请日：2008-02-19

申请人： Freescale Semiconductor, Inc.

发明人： PERKINS, Geoffrey W.

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  G11C17/16 ,  G11C17/18 ,  H03K19/17748 ,  H03K19/17764 ,  H03K19/17768 ,  H03K19/1778

摘要： A device includes an anti-fuse (122) including a first electrode that can be selectively coupled to a first voltage reference (121) and a second electrode that can be selectively coupled to a second voltage reference (123). The device further includes a shunt transistor (124) including a first current electrode coupled to the first electrode of the anti-fuse (122), a second current electrode coupled to the second electrode of the anti-fuse (122), and a control electrode. The device additionally includes control logic (126) configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic (126) also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse.

摘要翻译： 一种器件包括反熔丝（122），该反熔丝包括可以选择性地耦合到第一电压参考（121）的第一电极和可以选择性地耦合到第二电压参考（123）的第二电极。 该器件还包括分流晶体管（124），该分流晶体管包括耦合到反熔丝（122）的第一电极的第一电流电极，耦合到反熔丝（122）的第二电极的第二电流电极以及控制器 电极。 该器件另外包括控制逻辑（126），其被配置为响应于旨在用于反熔丝的第一编程操作来禁用分路晶体管。 控制逻辑（126）还被配置为响应于不旨在用于反熔丝的第二编程操作来启用分路晶体管。

公开(公告)号：EP2140548A4

公开(公告)日：2010-06-09

申请号：EP07797815

申请日：2007-05-27

申请人： TABULA INC

发明人： TEIG STEVEN ,  SCHMIT HERMAN ,  REDGRAVE JASON ,  HUANG RANDY RENFU

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

公开(公告)号：EP1864296A4

公开(公告)日：2009-07-15

申请号：EP06748862

申请日：2006-03-29

申请人： CAUTHEN RES GROUP INC

发明人： FANT KARL M

IPC分类号： G06F15/78 ,  G06F15/80

CPC分类号： G11C19/00 ,  G06F15/8023 ,  H03K19/17704

摘要： Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.