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    Programmable high-speed I/O interface
    2.
    发明公开
    Programmable high-speed I/O interface 有权
    Programmierbare Hochgeschwindigkeits-E / A-Schnittstelle

    公开(公告)号：EP2226941A2

    公开(公告)日：2010-09-08

    申请号：EP09013169.9

    申请日：2002-08-28

    申请人： Altera Corporation

    发明人： Wang, Boonie I. ,  Sung, Chiakang ,  Huang, Joseph ,  Nguyen, Khai ,  Pan, Philip

    IPC分类号： H03K19/177 ,  H03K19/0185

    CPC分类号： H03K19/17744 ,  H03K19/0175 ,  H03K19/017509 ,  H03K19/017581 ,  H03K19/1774 ,  H03K19/17788

    摘要： The present application comprises an integrated circuit comprising a differential input buffer (791) having a first input coupled to a first pad (710,1210) and a second input coupled to a second pad (720,1220); a first single-ended input buffer (751) having an input coupled to the first pad (720,1220); a second single-ended input buffer (756) having an input coupled to the second pad (720,1220);a first single-ended output buffer (771) having an output coupled to the first pad (710,1210); a second single-ended output buffer (776) having an output coupled to the second pad (720,1220); a serial-to-parallel converter (725) having an input coupled to an output of the differential input buffer (791); and a parallel-to-serial converter (715) having an output coupled to an input of the first single-ended output buffer (771).
    The present application further comprises a method of providing and receiving signals.

    摘要翻译： 本申请包括集成电路，其包括具有耦合到第一焊盘（710,1210）的第一输入和耦合到第二焊盘（720,1220）的第二输入的差分输入缓冲器（791）; 具有耦合到所述第一焊盘（720,1220）的输入的第一单端输入缓冲器（751）; 具有耦合到所述第二焊盘（720,1220）的输入的第二单端输入缓冲器（756）;具有耦合到所述第一焊盘（710,1210）的输出的第一单端输出缓冲器（771）; 具有耦合到所述第二焊盘（720,1220）的输出的第二单端输出缓冲器（776）; 具有耦合到差分输入缓冲器（791）的输出的输入的串并转换器（725）; 以及具有耦合到第一单端输出缓冲器（771）的输入的输出的并行到串行转换器（715）。 本申请还包括提供和接收信号的方法。

    SPARE CELL ARCHITECTURE FOR FIXING DESIGN ERRORS IN MANUFACTURED INTEGRATED CIRCUITS
    7.
    发明公开
    SPARE CELL ARCHITECTURE FOR FIXING DESIGN ERRORS IN MANUFACTURED INTEGRATED CIRCUITS 审中-公开
    备用单元体结构的施工缺陷对集成电路修复

    公开(公告)号：EP1568133A1

    公开(公告)日：2005-08-31

    申请号：EP03759356.3

    申请日：2003-09-17

    申请人： ATMEL CORPORATION

    发明人： VERGNES, Alain

    IPC分类号： H03K19/003 ,  H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1774 ,  H03K19/17796

    摘要： A fully self-sufficient configurable spare gate cell (11) has two types of inputs: a functional input bus (FIN; 10,12; 68; 76) and an equation input bus (EQ.IN; 70; 78), whereby the spare gate cell can be transformed into any sum of product operator by the assertion of certain signals to the equation input bus. The spare cell may also include a D flip-flop (38; 84). In a spare state, the functional input buses are connected to an area of pre-defined logic (64) where the need for bug fixes are high. Thus, the spare cell would be automatically placed close to the bug-fix area during the place-and-route phase of chip design, thereby reducing the need to look for routing channels.

    In-system programmable interconnect circuit
    9.
    发明公开
    In-system programmable interconnect circuit 失效
    Im系统程序员Verbindungsschaltkreis

    公开(公告)号：EP0871292A1

    公开(公告)日：1998-10-14

    申请号：EP98302420.9

    申请日：1998-03-30

    申请人： LATTICE SEMICONDUCTOR CORPORATION

    发明人： Kopec, Stanley J., Jr. ,  Wang, Cheng-Yuan Michael ,  Farmer, Jerome Connelly ,  Tsui, Cyrus Y.

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1774 ,  H03K19/17744

    摘要： A programmable interconnect circuit includes multiple input/output cells, each corresponding to an input/output pin, and a global routing resource for routing signals received at the input pins to be output as output signals at output and bi-directional pins. The signals routed in the global routing resource can include multiplexer control signals, clock signals and output enable signals for controlling dynamic signal switching. The global routing resource allows high static routability.

    摘要翻译： 可编程互连电路包括多个输入/输出单元，每个单元对应于输入/输出引脚，以及全局布线资源，用于将在输入引脚处接收的信号路由输出作为输出和双向引脚上的输出信号。 在全局路由资源中路由的信号可以包括用于控制动态信号切换的多路复用器控制信号，时钟信号和输出使能信号。 全局路由资源允许高静态可路由性。

    Configurable logic array
    10.
    发明公开
    Configurable logic array 失效
    可配置的逻辑阵列

    公开(公告)号：EP0776093A3

    公开(公告)日：1997-06-18

    申请号：EP97101407.1

    申请日：1994-06-01

    申请人： PILKINGTON MICRO-ELECTRONICS LIMITED

    发明人： Jones, Gareth James ,  Work, Gordon Stirling

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736 ,  H03K19/1736 ,  H03K19/17704 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17796

    摘要： A configurable semi-conductor integrated circuit comprising an area thereof formed with a plurality of logic circuits at discrete sites or cells (cc) respectively defining a matrix array of cells. The matrix array of cells is subdivided at least into zones (each comprising a matrix array of cells) and further comprising a porting arrangement for each zone and a hierarchical routing resource structure comprising:-
    (i) global connection parts (G, X) having selectable connections with the porting arrangement of each zone, (ii) medium connection parts (M) extending from the porting arrangement and selectably connectable with at least some of the cells in a zone, and (iii) local direct connection paths comprising a restricted signal translation system. The application also describes a configurable semi-conductor integrated circuit comprising a matrix array of core cells (cc), each of the cells having a first simple function in common and at least one subsidiary function, there being at least two different subsidiary functions, the core cells being grouped in tiles comprising a matrix array of the core cells smaller than the whole array and wherein each tile has at least one of each different subsidiary functions and wherein the tiles of core cells are arranged so as to uniformly cover the array. Preferably there are fours cells to a tile and the preferred subsidiary function are:- wired-OR, XOR, D-type flip flop and latch function. The above features are preferably combined to produce a particularly advantageous construction of configurable semi-conductor integrated circuit.

    摘要翻译： 一种可配置的半导体集成电路，包括其分离区域形成有多个逻辑电路的区域或分别限定单元矩阵阵列的单元（cc）。 矩阵阵列的单元至少被细分为区域（每个区域包括单元的矩阵阵列）并且还包括用于每个区域的端口布置以及分层布线资源结构，该分层布线资源结构包括：（i）全局连接部分（G，X） （ii）从端口装置延伸并且可选择地与区域中的至少一些单元连接的介质连接部分（M），以及（iii）包括限制信号的局部直接连接路径 翻译系统。 本申请还描述了一种可配置的半导体集成电路，其包括核心单元（cc）的矩阵阵列，每个单元具有共同的第一简单功能和至少一个辅助功能，存在至少两个不同的辅助功能， 核心单元被分组在包括核心单元的矩阵阵列的瓦片中，所述核心单元的矩阵阵列小于整个阵列，并且其中每个瓦片具有每个不同的附属功能中的至少一个，并且其中核心单元的瓦片被布置为均匀地覆盖阵列。 优选地，四个单元格对应于瓦片，并且优选的辅助功能是： - 线或门，XOR，D型触发器和闩锁功能。 上述特征优选地被组合以产生可配置的半导体集成电路的特别有利的构造。