公开(公告)号：EP0098163A3

公开(公告)日：1986-04-16

申请号：EP83303760

申请日：1983-06-29

申请人： FUJITSU LIMITED

发明人： Sato, Shinji

IPC分类号： H01L27/02

CPC分类号： H03K19/17744 ,  H01L21/82 ,  H01L27/11807 ,  H01L2924/0002 ,  H03K5/023 ,  H03K19/09425 ,  H03K19/09429 ,  H03K19/0948 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796 ,  H01L2924/00

摘要： A gate-array chip comprises a plurality of basic-cell arrays (40) arranged parallel to one another on a semiconductor bulk (60), and a plurality of impurity regions (50) formed on the semiconductor bulk and in regions between the basic-cell arrays. The impurity regions and part of the basic-cell arrays are adapted to form input/output circuits (10) whereby the gate-array chip can be divided into several chips each having a desired size and a desired number of gates.

公开(公告)号：EP0093003A2

公开(公告)日：1983-11-02

申请号：EP83302324.5

申请日：1983-04-22

申请人： FUJITSU LIMITED

发明人： Matsumura, Nobutake Nisshin Dai-2 ,  Sato, Shinji

IPC分类号： H01L27/02

CPC分类号： H01L22/00 ,  H01L24/05 ,  H01L27/11898 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： Gate array LSI's are produced with the aid of a standard layout pattern defining a basic cell array region (2), on which internal cell arrays are arranged, and a peripheral circuit region (3), arranged on the periphery of the basic cell array region. The peripheral circuit region comprises input/output cell regions (7), for constructing an input buffer circuit and a part of an output circuit, and a general purpose cell array region (4) which can be used for constructing remaining parts of the output buffer circuit. Where the general purpose cell array region is not used in the construction of such a buffer circuit it can be used for constructing various other desired circuits. Thus greater design flexibility is made available.

摘要翻译： 门阵列LSI借助于限定布置有内部单元阵列的基本单元阵列区域（2）的标准布局图案和布置在基本单元阵列区域的外围的外围电路区域（3） 。 外围电路区域包括用于构成输入缓冲电路和输出电路的一部分的输入/输出单元区域（7）和可用于构造输出缓冲器的剩余部分的通用单元阵列区域（4） 电路。 在通用单元阵列区域不用于构造这种缓冲电路的情况下，其可用于构建各种其它期望的电路。 因此，提供更大的设计灵活性。