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19 条记录 (耗时 0.013 秒)

    Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
    13.
    发明公开
    Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism 失效
    由具有一个本地存储器和一种改进的数据传输机制的处理器元件并行计算机。

    公开(公告)号：EP0326164A2

    公开(公告)日：1989-08-02

    申请号：EP89101462.3

    申请日：1989-01-27

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo

    IPC分类号： G06F15/16 ,  G06F9/44

    CPC分类号： G06F15/163

    摘要： In a parallel computer, there are provided a plurality of processor elements (1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor elements; a memory area constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit (4), and a memory constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of said plurality of reception data areas in response to the data received from said network, and writing the valid data tag into one of said plurality of reception data areas, said receiving circuit being parallel-operated with said processor; and, an access circuit for reading both the data and tag from one of the reception data areas determined by said data identifier and from the corresponding tag areas in response to the data identifier designated by the instruction which is produced from said program for requiring the data reception, and for repeatedly reading the tag and data from the tag area and reception data area until the valid data tag is read out from the tag area in case that the read tag corresponds to the invalid data tag.

    摘要翻译： 在并行计算机中，有通过网络（2）提供相互连接的处理器元件（1-1到1-n）的多元性; 每个所述处理器元件的包括本地存储器（6），用于保持程序和与其相关的数据，处理器（3），用于在所述程序在指令执行，电路（5），用于传递环的数据到其它处理器的元件，并且 用于接收从其他的处理器元件发送的数据的电路（4）; 用于暂时存储接收电路（4）由所述接收的数据构建的接收数据区中的多个存储区域，并构建一天区域的多个存储器，提供给每个接收数据区域，用于存储有效的数据的标签 或无效数据标签指示在做相应的接收数据区的数据是有效还是无效; 发送用于发送的数据是反式与mitted附着由所述数据中的预定数据标识符的电路（5）; 从所述网络接收到用于将数据写入接收数据区的所述多个中的一个响应于所述数据的接收电路，和写入有效的数据的标签到接收数据区的所述多个，所述一个与接收电路被并行操作的 所述处理器; 和访问电路，用于响应于由所述指令所指定的数据的标识符从确定性由所述数据标识符和从相应的天地区开采的接收数据区的一个既读取数据和标签，其是从所述程序产生的所有需要​​数据 接待处，并直至有效数据标签，从标签区域的情况下，读出没有读取的标签对应于无效数据标签重复读取从标签区域和接收数据区域的标签和数据。

    Method of sorting on distributed database system and method of accessing thereto
    17.
    发明公开
    Method of sorting on distributed database system and method of accessing thereto 失效
    在einer verteilten Datei und Zugangsverfahren dazu的Sortierverfahren。

    公开(公告)号：EP0522488A2

    公开(公告)日：1993-01-13

    申请号：EP92111457.5

    申请日：1992-07-07

    申请人： HITACHI, LTD.

    发明人： Fujiwara, Shinji, Hitachi Daivon Kyoshinryo B305 ,  Shintani, Yooichi ,  Nagasaka, Mitsuru ,  Hamanaka, Naoki ,  Suzuki, Mikiko

    IPC分类号： G06F7/24

    CPC分类号： G06F7/24 ,  Y10S707/99937

    摘要： A sorting method used with a distributed database having a plurality of first processors (203) for holding partial records of database divided into a plurality of portions and a host processor (201) for accessing to each of the first processors, comprising the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors (204) in the first processors (203); transferring the key values of the plurality of records of the portions of the database held in the first processors (203), and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors (204) to produce key tables (212) in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.

    摘要翻译： 一种与分布式数据库一起使用的排序方法，所述分布式数据库具有多个第一处理器（203），用于保存划分成多个部分的数据库的部分记录，以及主处理器（201），用于访问每个第一处理器，包括以下步骤： 在所述第一处理器（203）中分配多个区段，所述多个区段将所述数据库的记录的键值的分配范围分割成多个第二处理器（204）; 将保存在第一处理器（203）中的数据库的部分的多个记录的键值和将记录的存储位置的信息传送到具有记录的键值的部分的第二处理器 属于，分配; 以及对已经接收的多个密钥值进行排序，以生成密钥表（212），其中用于表示已经接收到的记录的存储位置的信息与排序的密钥一起被注册 值，作为排序结果。

    Multiple processor system
    18.
    发明公开
    Multiple processor system 失效
    具有来自程序识别代码的转换器到处理器识别代码的并行计算机系统

    公开(公告)号：EP0255857A3

    公开(公告)日：1990-10-31

    申请号：EP87107576.8

    申请日：1987-05-22

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omada, Koichiro ,  Nagashima, Shigeo

    IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/54 ,  G06F15/161

    摘要： A parallel processor system is disclosed which com­prises a plurality of processors (1) each for executing at least one of a plurality of mutually associated programs and a transfer circuit (3) connected to the processors, for transferring the data outputted from any one of the pro­grams during execution of one program by any one of the processors (1) to other processors (1) to which a receiving program is allotted, in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.