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29 条记录 (耗时 0.012 秒)

    Computer for synchronized read and write of vector data
    4.
    发明公开
    Computer for synchronized read and write of vector data 失效
    用于同步读取和写入矢量数据的计算机

    公开(公告)号：EP0301593A3

    公开(公告)日：1989-11-29

    申请号：EP88112385.5

    申请日：1988-07-29

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omoda, Koichiro ,  Nagashima, Shigeo ,  Nakagoshi, Junji ,  Ojima, Kazuo

    IPC分类号： G06F15/06

    CPC分类号： G06F15/8092 ,  G06F15/8084

    摘要： A computer comprises a circuit (107) for writing a group of ordered data elements into a main storage (3 ), a circuit (108) for reading said group of data from the main storage ( 3), and a circuit (1, 2, 203-1) connected to the writing circuit (107) and to the reading circuit (108) for ensuring the sequence of main storage references between said writing circuit (107) and said reading circuit (108) such that said reading circuit (108) will not read the data elements that have not yet been written by said writing circuit (107) among said group of data elements.

    Multiple processor system
    5.
    发明公开
    Multiple processor system 失效
    Mehrfachrechnersystem。

    公开(公告)号：EP0255857A2

    公开(公告)日：1988-02-17

    申请号：EP87107576.8

    申请日：1987-05-22

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omada, Koichiro ,  Nagashima, Shigeo

    IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/54 ,  G06F15/161

    摘要： A parallel processor system is disclosed which com­prises a plurality of processors (1) each for executing at least one of a plurality of mutually associated programs and a transfer circuit (3) connected to the processors, for transferring the data outputted from any one of the pro­grams during execution of one program by any one of the processors (1) to other processors (1) to which a receiving program is allotted, in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

    摘要翻译： 公开了一种并行处理器系统，其包括多个处理器（1），每个处理器用于执行多个相互关联的程序中的至少一个和连接到处理器的传送电路（3），用于传送从 响应于由一个处理器在一个程序的执行期间输出的程序识别码来识别接收到的程序，在由一个处理器（1）中的任何一个执行一个程序到另一个处理器（1）的程序中， 程序。

    Data processing apparatus
    10.
    发明公开
    Data processing apparatus 失效
    数据处理设备

    公开(公告)号：EP0141908A3

    公开(公告)日：1987-12-23

    申请号：EP84108740

    申请日：1984-07-24

    申请人： HITACHI, LTD.

    发明人： Torii, Schunichi ,  Nagashima, Shigeo ,  Omoda, Koichiro

    IPC分类号： G06F15/347

    CPC分类号： G06F15/8076 ,  G06F9/3885

    摘要： @ A data processing apparatus comprises a plurality of sub-systems (30a-30d) each including at least one arithmetic unit (38a-38d), a plurality of registers (35a-35d), a first selector (33a-33d) for receiving vector data and selectively outputting the input data to the registers, and a second selector (34a-34d) for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in other sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit (10), and the data output from the main storage unit is supplied to the first selector in at least one sub-system.