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19 条记录 (耗时 0.014 秒)

    Method of sorting on distributed database system and method of accessing thereto
    3.
    发明公开
    Method of sorting on distributed database system and method of accessing thereto 失效
    分配数据库系统的方法和接入方法

    公开(公告)号：EP0522488A3

    公开(公告)日：1993-05-26

    申请号：EP92111457.5

    申请日：1992-07-07

    申请人： HITACHI, LTD.

    发明人： Fujiwara, Shinji, Hitachi Daivon Kyoshinryo B305 ,  Shintani, Yooichi ,  Nagasaka, Mitsuru ,  Hamanaka, Naoki ,  Suzuki, Mikiko

    IPC分类号： G06F7/24

    CPC分类号： G06F7/24 ,  Y10S707/99937

    摘要： A sorting method used with a distributed database having a plurality of first processors (203) for holding partial records of database divided into a plurality of portions and a host processor (201) for accessing to each of the first processors, comprising the steps of: assigning a plurality of sections into which the distribution range of key values of records of the database is partitioned to a plurality of second processors (204) in the first processors (203); transferring the key values of the plurality of records of the portions of the database held in the first processors (203), and information for representing storage positions of the records to the second processors to which the sections of the key values, to which the records belong, are assigned; and sorting the plurality of key values, which have been received, in the second processors (204) to produce key tables (212) in which the information for representing the storage positions of the records which has been received is registrated together with the sorted key values, as the sorting result.

    Computer for synchronized read and write of vector data
    4.
    发明公开
    Computer for synchronized read and write of vector data 失效
    ReennerfürSynchronisiertes Lesen und Schreiben von vektoriellen Daten。

    公开(公告)号：EP0301593A2

    公开(公告)日：1989-02-01

    申请号：EP88112385.5

    申请日：1988-07-29

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omoda, Koichiro ,  Nagashima, Shigeo ,  Nakagoshi, Junji ,  Ojima, Kazuo

    IPC分类号： G06F15/06

    CPC分类号： G06F15/8092 ,  G06F15/8084

    摘要： A computer comprises a circuit (107) for writing a group of ordered data elements into a main storage (3 ), a circuit (108) for reading said group of data from the main storage ( 3), and a circuit (1, 2, 203-1) connected to the writing circuit (107) and to the reading circuit (108) for ensuring the sequence of main storage references between said writing circuit (107) and said reading circuit (108) such that said reading circuit (108) will not read the data elements that have not yet been written by said writing circuit (107) among said group of data elements.

    摘要翻译： 计算机包括用于将一组有序数据元素写入主存储器（3）的电路（107），用于从主存储器（3）读取所述数据组的电路（108）和电路（1,2） ，203-1）连接到写入电路（107）和读取电路（108），用于确保所述写入电路（107）和所述读取电路（108）之间的主存储基准序列，使得所述读取电路（108） ）将不会读取所述写入电路（107）尚未被写入所述数据元素组中的数据元素。

    Parallel computer with distributed shared memories and distributed task activating circuits
    5.
    发明公开
    Parallel computer with distributed shared memories and distributed task activating circuits 失效
    并行计算机具有分布，共享存储器和分布式任务激活电路。

    公开(公告)号：EP0258736A2

    公开(公告)日：1988-03-09

    申请号：EP87111988.9

    申请日：1987-08-18

    申请人： HITACHI, LTD.

    发明人： Muramatsu, Akira ,  Sakoda, Kousuke ,  Yoshihara, Ikuo ,  Nakao, Kazuo ,  Nohmi, Makoto ,  Hamanaka, Naoki ,  Nagashima, Shigeo ,  Tanaka, Teruo

    IPC分类号： G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/5016 ,  G06F8/451 ,  G06F2209/484

    摘要： In accessing a memory, each element processor (100) executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruc­tion is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-­mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

    摘要翻译： 在访问的存储器，每个元件处理器（100）执行的程序设计以便指定到属于预定将localAddress面积为每个元件处理器地址。 当一个存储器写指令是通过在元件处理器执行时，它是如果由所述指令所指定的存储器地址与预定的地址一致检出。 如果检测到的，预定的地址属于另一元件处理器的局部地址空间和分配给该第一次提及的预定地址，并写入响应于所述写指令的数据，被发送到其他元件处理器以指示数据是 写入其中的复制数据。 下一任务将被执行决定unabhängig每个元件处理器。

    Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
    7.
    发明公开
    Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism 失效
    具有本地存储器和增强数据传输机制的处理器元件的并行计算机

    公开(公告)号：EP0326164A3

    公开(公告)日：1990-06-13

    申请号：EP89101462.3

    申请日：1989-01-27

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo

    IPC分类号： G06F15/16 ,  G06F9/44

    CPC分类号： G06F15/163

    摘要： In a parallel computer, there are provided a plurality of processor elements (1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor elements; a memory area constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit (4), and a memory constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of said plurality of reception data areas in response to the data received from said network, and writing the valid data tag into one of said plurality of reception data areas, said receiving circuit being parallel-operated with said processor; and, an access circuit for reading both the data and tag from one of the reception data areas determined by said data identifier and from the corresponding tag areas in response to the data identifier designated by the instruction which is produced from said program for requiring the data reception, and for repeatedly reading the tag and data from the tag area and reception data area until the valid data tag is read out from the tag area in case that the read tag corresponds to the invalid data tag.

    Computer for synchronized read and write of vector data
    8.
    发明公开
    Computer for synchronized read and write of vector data 失效
    用于同步读取和写入矢量数据的计算机

    公开(公告)号：EP0301593A3

    公开(公告)日：1989-11-29

    申请号：EP88112385.5

    申请日：1988-07-29

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omoda, Koichiro ,  Nagashima, Shigeo ,  Nakagoshi, Junji ,  Ojima, Kazuo

    IPC分类号： G06F15/06

    CPC分类号： G06F15/8092 ,  G06F15/8084

    摘要： A computer comprises a circuit (107) for writing a group of ordered data elements into a main storage (3 ), a circuit (108) for reading said group of data from the main storage ( 3), and a circuit (1, 2, 203-1) connected to the writing circuit (107) and to the reading circuit (108) for ensuring the sequence of main storage references between said writing circuit (107) and said reading circuit (108) such that said reading circuit (108) will not read the data elements that have not yet been written by said writing circuit (107) among said group of data elements.

    Multiple processor system
    9.
    发明公开
    Multiple processor system 失效
    Mehrfachrechnersystem。

    公开(公告)号：EP0255857A2

    公开(公告)日：1988-02-17

    申请号：EP87107576.8

    申请日：1987-05-22

    申请人： HITACHI, LTD.

    发明人： Hamanaka, Naoki ,  Tanaka, Teruo ,  Omada, Koichiro ,  Nagashima, Shigeo

    IPC分类号： G06F9/44 ,  G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/54 ,  G06F15/161

    摘要： A parallel processor system is disclosed which com­prises a plurality of processors (1) each for executing at least one of a plurality of mutually associated programs and a transfer circuit (3) connected to the processors, for transferring the data outputted from any one of the pro­grams during execution of one program by any one of the processors (1) to other processors (1) to which a receiving program is allotted, in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

    摘要翻译： 公开了一种并行处理器系统，其包括多个处理器（1），每个处理器用于执行多个相互关联的程序中的至少一个和连接到处理器的传送电路（3），用于传送从 响应于由一个处理器在一个程序的执行期间输出的程序识别码来识别接收到的程序，在由一个处理器（1）中的任何一个执行一个程序到另一个处理器（1）的程序中， 程序。

    A processor with cache memory used in receiving data from other processors
    10.
    发明公开
    A processor with cache memory used in receiving data from other processors 失效
    Prozessor und Cache-Speicher zum Empfang von Daten anderer Prozessoren。

    公开(公告)号：EP0588369A1

    公开(公告)日：1994-03-23

    申请号：EP93115106.2

    申请日：1993-09-20

    申请人： HITACHI, LTD.

    发明人： Higuchi, Tatsuo ,  Hamanaka, Naoki

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0813

    摘要： A processor (1) for a multiprocessor system, such as a parallel processor system, connected to a network (2) has a sending unit (11) and a receiving unit (12) for transferring and receiving data to and from the network (2) as well as receive cache (22) and main cache. When data are received from the network (2), it is determined whether a hit or miss occurs to the main cache (21) and receive cache (22), respectively. If a hit to the receive cache (22) occurs, then the receive cache controller (14) stores the data directly in the receive cache (22) as it is received. When a hit to the main cache (21) occurs, an intercache transfer is executed for transferring the hit block in the main cache (21) to the receive cache (22) so that the data can be stored in the receive cache (22). When an instruction processor (10) requests access to data held in the receive cache (22), the data are retrieved to the instruction processor (10) and at the same time transferred to the main cache (21).

    摘要翻译： 用于连接到网络（2）的诸如并行处理器系统的多处理器系统的处理器（1）具有发送单元（11）和用于从网络（2）传送和接收数据的发送单元（11）和接收单元（12） ）以及接收缓存（22）和主缓存。 当从网络（2）接收到数据时，确定是否发生命中或未命中到主缓存（21）和接收缓存（22）。 如果发生对接收缓存（22）的命中，则接收高速缓存控制器（14）在接收高速缓存（22）中直接存储数据。 当发生对主缓存（21）的命中时，执行中间传送以将主缓存（21）中的命中块传送到接收缓存（22），使得数据可以存储在接收缓存（22）中， 。 当指令处理器（10）请求对接收高速缓存（22）中保存的数据的访问时，将数据检索到指令处理器（10）并同时传送到主缓存器（21）。