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42 条记录 (耗时 0.013 秒)

    A content addressable memory cell
    13.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP1526547A1

    公开(公告)日：2005-04-27

    申请号：EP03103898.7

    申请日：2003-10-22

    申请人： STMicroelectronics S.r.l. ,  Ovonyx Inc.

    发明人： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： G11C15/04

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    14.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件，特别是相变存储器，具有硅化方法

    公开(公告)号：EP1439579A1

    公开(公告)日：2004-07-21

    申请号：EP03425017.5

    申请日：2003-01-15

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC分类号： H01L21/8234 ,  H01L21/8239

    CPC分类号： H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    摘要翻译： 的方法worin到绝缘区域（13）在一个主体中形成至少围绕到一半导体主体的阵列部分（51）（10）; 半导体材料的栅极区（16）形成在所述半导体主体的一个电路部分（51）的顶部（10）; 的第一硅化物保护掩模（52）是形成在阵列部分的顶部上; 栅极区（16）和所述电路部（51）的有源区（43）被硅化并且所述第一硅化物保护掩模（52）被去除。 第一硅化物保护掩模（52）是多晶硅，并且与所述栅极区域（16）同时形成。 覆盖所述第一硅化物保护掩模（52）的介电材料的第二硅化物保护掩模（53）的栅极区（16）的硅化之前形成。 第二硅化物保护掩模（53）与形成尾盘反弹到栅极区域（16）间隔件（41）同时形成。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    15.
    发明公开
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    Zellenanordnung mit Bipolar-Auswahl-Transistor和Herstellungsverfahren

    公开(公告)号：EP1408550A1

    公开(公告)日：2004-04-14

    申请号：EP02425605.9

    申请日：2002-10-08

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

    IPC分类号： H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    摘要： A cell array (1) is formed by a plurality of cells (2) including each a selection bipolar transistor (4) and a storage component (3). The cell array is formed in a body (10) including a common collector region (11) of P type; a plurality of base regions (12) of N type, overlying the common collector region (11); a plurality of emitter regions (14) of P type formed in the base regions; and a plurality of base contact regions (15) of N type and a higher doping level than the base regions, formed in the base regions (12; 42), wherein each base region (12) is shared by at least two adjacent bipolar transistors (20).

    摘要翻译： 电池阵列包括设置在主体（10）中的P型公共集电极区域（11）上的N型基极区域（12）的数量。 在基极区域中形成P型发射极区域（14）和N型基极接触区域（15），使得基极接触区域的掺杂水平高于基极区域的掺杂水平，并且每个基极区域由 至少两个双极晶体管（20）。 电池阵列制造过程中还包括独立权利要求。

    Phase change memory cell and manufacturing method thereof using minitrenches
    16.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    相变存储单元，并且借助于minitrenches及其制造方法

    公开(公告)号：EP1339110A9

    公开(公告)日：2004-01-28

    申请号：EP02425087.0

    申请日：2002-02-20

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    A memory device
    18.
    发明公开
    A memory device 有权

    公开(公告)号：EP1306852A3

    公开(公告)日：2004-03-10

    申请号：EP02078984.8

    申请日：2002-09-27

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC分类号： G11C11/34 ,  G11C16/02

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    摘要： A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof
    19.
    发明公开
    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof 有权
    亚光刻接触结构，具有优化的加热结构相变存储单元，以及它们的制备方法

    公开(公告)号：EP1339103A1

    公开(公告)日：2003-08-27

    申请号：EP02425088.8

    申请日：2002-02-20

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： An electronic semiconductor device has a sublithographic contact area (45, 58) between a first conductive region (22) and a second conductive region (38). The first conductive region (22) is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area (45, 58). The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

    摘要翻译： 一种电子半导体器件具有第一导电区（22）和一个第二导电区（38）之间的亚光刻的接触面积（45，58）。 第一导电区（22）是杯形，并具有垂直壁延伸，在俯视图中，沿着细长形状的封闭线。 一个第一导电区域的壁的形成第一薄壁部，并且具有在第一方向上的第一尺寸。 第二导电区域（38）具有在第二方向上的第二亚光刻尺寸（X）横向于第一尺寸的第二薄壁部（38A）。 所述第一和第二导电区域在其薄的部分直接电接触，并形成亚光刻接触区域（45，58）。 细长形状在第一方向上的矩形和椭圆形的细长之间选择。 因此，接触区域的尺寸，即使在掩模之间的小的未对准的存在保持大致恒定，限定导电区域。