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    Process for manufacturing a memory device having selector transistors for storage elements and memory device fabricated thereby
    2.
    发明公开
    Process for manufacturing a memory device having selector transistors for storage elements and memory device fabricated thereby 有权
    一种用于制造具有用于存储元件的选择晶体管的蓄电装置，以及相应产生的存储装置的过程

    公开(公告)号：EP1475840A1

    公开(公告)日：2004-11-10

    申请号：EP03425292.4

    申请日：2003-05-07

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Pellizzer, Fabio ,  Bez, Roberto

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126

    摘要： A process for manufacturing a memory device having selector bipolar transistors (25) for storage elements (65), includes the steps of: in a semiconductor body (20), forming at least a selector transistor (25), having at least an embedded conductive region (26), and forming at least a storage element (65), stacked on and electrically connected to the selector transistor (25); moreover, the step of forming at least a selector transistor (25) includes forming at least a raised conductive region (35, 36) located on and electrically connected to the embedded conductive region (26).

    摘要翻译： 一种用于制造具有存储元件选择双极型晶体管（25）（65）的存储器器件的方法包括以下步骤：在半导体本体（20），形成至少上嵌入的导电至少具有选择晶体管（25） 区域（26），和至少形成存储元件（65），堆叠​​在并且电连接到选择晶体管（25）; 更完了，形成至少一个选择晶体管（25）的步骤包括形成至少位于并电连接到嵌入的导电区域（26）的凸起的导电区域（35，36）。

    Small area contact region, high efficiency phase change memory cell and fabrication method thereof
    3.
    发明公开
    Small area contact region, high efficiency phase change memory cell and fabrication method thereof 审中-公开
    小面积接触区域，高效率相变存储器元件及其制造方法

    公开(公告)号：EP1318552A1

    公开(公告)日：2003-06-11

    申请号：EP01128461.9

    申请日：2001-12-05

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Bez, Roberto ,  Pellizzer, Fabio ,  Riva, Caterina ,  Zonca, Romina

    IPC分类号： H01L45/00 ,  G11C11/34 ,  H01L27/24

    CPC分类号： G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691 ,  Y10S438/947

    摘要： A contact structure (30) in an electronic semiconductor device, including a first conducting region (31) having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region (32) having a second thin portion (32a) with a second sublithographic dimension in a second direction transverse to said first direction; the first and second conducting regions being in direct electrical contact at the first and second thin portions and defining a contact area (33) having a sublithografic extension, lower than 100 nm, preferably about 20 nm. The thin sublithographic portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer (34); the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic hard mask opening that is used to etch a mold opening (40) in a mold layer (38) and filling the mold opening.

    摘要翻译： 在半导体电子器件，其包括具有在第一方向上的第一亚光刻尺寸的第一薄壁部的第一导电区域（31）的接触结构（30）; 具有在第二方向上横向于所述第一方向的第二亚光刻尺寸的第二薄壁部（32A）的第二导电区（32）; 第一和第二导电区域在所述第一和第二薄膜部分直接电接触和限定具有sublithografic延伸的接触区域（33），低于100nm，优选约20nm。薄亚光刻的部分获得使用沉积代替 光刻的：所述第一薄壁部的设置于在第一电介质层（34）中的开口的壁; 所述第二薄壁部是通过在第一划界层的垂直壁罢免牺牲区域，在所述牺牲区域的自由侧罢免第二划界层，去除牺牲区域以形成亚光刻硬掩模开口获得并用于蚀刻 在模制层（38）和填充所述模具开口的模具开口（40）。

    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step
    6.
    发明公开
    Process for manufacturing a memory device, in particular a phase change memory, including a silicidation step 有权
    一种用于制造存储器件的方法，特别是相变存储器，所述方法包括硅化

    公开(公告)号：EP1439579A9

    公开(公告)日：2005-02-09

    申请号：EP03425017.5

    申请日：2003-01-15

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Pellizzer, Fabio ,  Bez, Roberto ,  Tosi, Marina

    IPC分类号： H01L21/8234 ,  H01L21/8239

    CPC分类号： H01L21/823835 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    摘要： A process wherein an insulating region (13) is formed in a body at least around an array portion (51) of a semiconductor body (10); a gate region (16) of semiconductor material is formed on top of a circuitry portion (51) of the semiconductor body (10); a first silicide protection mask (52) is formed on top of the array portion; the gate region (16) and the active areas (43) of the circuitry portion (51) are silicided and the first silicide protection mask (52) is removed. The first silicide protection mask (52) is of polysilicon and is formed simultaneously with the gate region (16). A second silicide protection mask (53) of dielectric material covering the first silicide protection mask (52) is formed before silicidation of the gate region (16). The second silicide protection mask (53) is formed simultaneously with spacers (41) formed laterally to the gate region (16).

    Phase change memory cell and manufacturing method thereof using minitrenches
    7.
    发明公开
    Phase change memory cell and manufacturing method thereof using minitrenches 有权
    Phasenwechsel-Speicherzelle sowie deren Herstellungsverfahren手套Minigräben

    公开(公告)号：EP1339110A1

    公开(公告)日：2003-08-27

    申请号：EP02425087.0

    申请日：2002-02-20

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Bez, Roberto ,  Pellizzer, Fabio ,  Tosi, Marina ,  Zonca, Romina

    IPC分类号： H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y) ; and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first thin portion (22) and the second thin portion (38a) are in direct electrical contact and define a contact area (58) of sublithographic extension. The second thin portion (38a) is delimited laterally by oxide spacer portions (55a) surrounded by a mold layer (49) which defines a lithographic opening (51). The spacer portions (55a) are formed after forming the lithographic opening, by a spacer formation technique.

    摘要翻译： 相变存储单元（5）由电阻元件（22）和相变材料的存储区域（38）形成。 电阻元件具有在第一方向（Y）上具有第一亚光刻尺寸的第一薄部分。 并且所述存储区域（38）具有在横向于所述第一尺寸的第二方向（X）上具有第二亚光刻尺寸的第二薄部分（38a）。 第一薄部分（22）和第二薄部分（38a）直接电接触并限定亚光刻延伸部分的接触区域（58）。 第二薄部分（38a）由限定光刻开口（51）的模制层（49）围绕的氧化物间隔部分（55a）横向限定。 间隔物部分（55a）通过间隔物形成技术在形成光刻开口之后形成。

    A content addressable memory cell
    8.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP2261928A3

    公开(公告)日：2011-04-20

    申请号：EP10183801.9

    申请日：2003-10-22

    申请人： STMicroelectronics S.r.l. ,  Ovonyx Inc.

    发明人： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： G11C15/04 ,  G11C14/00

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    A content addressable memory cell
    9.
    发明公开
    A content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：EP2261928A2

    公开(公告)日：2010-12-15

    申请号：EP10183801.9

    申请日：2003-10-22

    申请人： STMicroelectronics S.r.l. ,  Ovonyx Inc.

    发明人： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： G11C15/04

    CPC分类号： G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    摘要： A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    摘要翻译： 一种用于非易失性内容可寻址存储器（100）的内容可寻址存储器单元（105），包括用于存储内容数字的非易失性存储装置（S1，S2，S），用于存储内容数字的选择输入（WLi; WLi，BLPj） 选择存储器单元，用于接收搜索数字（BLRj，BLLj）的搜索输入以及用于将搜索数字与内容数字进行比较并用于驱动存储器单元的匹配输出（MLi）以便发信号 内容数字和搜索数字之间的匹配。 非易失性存储装置包括至少一个用于以非易失性方式存储相应内容数字的相变存储器元件（S1，S2，S）。

    A memory device
    10.
    发明公开
    A memory device 有权
    存储设备

    公开(公告)号：EP1306852A2

    公开(公告)日：2003-05-02

    申请号：EP02078984.8

    申请日：2002-09-27

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC分类号： G11C11/34

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    摘要： A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    摘要翻译： 一种存储器件（100），包括多个存储器单元（Mh，k），在半导体材料（203）的芯片中形成的具有第一导电类型的多个绝缘第一区域（220h），至少一个第二区域 在每个第一区域中形成的第二导电类型的第二区域，每个第二区域和对应的第一区域之间的接点限定单向导通入元件（D h，k），用于当正向偏置时选择连接到第二区域的相应存储单元 以及用于接触每个第一区域的至少一个触点（225h） 在每个第一区域中形成多个存取元件，所述存取元件在不插入任何接触的情况下被分组成至少一个由多个相邻存取元件（Dh，k，Dh，k + 1）组成的子集，以及 该存储设备还包括用于同时正向偏置每个子集的访问元件的装置（110c，113,125）。