公开(公告)号：EP1271315B1

公开(公告)日：2018-06-20

申请号：EP02010606.8

申请日：2002-05-10

申请人： Microsoft Technology Licensing, LLC

发明人： Hsieh, Bor-Ming

IPC分类号： G06F9/48 ,  G06F7/32

CPC分类号： G06F9/4881 ,  G06F5/065 ,  G06F7/06 ,  G06F2205/064

摘要： Various implementations of the described subject associate a plurality of threads that are sorted based on thread priority with a run queue in a deterministic amount of time. The run queue includes a first plurality of threads, which are sorted based on thread priority. The second plurality of threads is associated with the run queue in a bounded, or deterministic amount of time that is independent of the number of threads in the associated second plurality. Thus, the various implementations of the described subject matter allow an operating system to schedule other threads for execution within deterministic/predetermined time parameters.

公开(公告)号：EP2862061A4

公开(公告)日：2016-12-21

申请号：EP13803692

申请日：2013-06-13

申请人： SOFT MACHINES INC

发明人： ABDALLAH MOHAMMAD

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F5/14 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F2205/063 ,  G06F2205/064

摘要： An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated beyond an actual physical size of the load store queue of the processor; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

摘要翻译： 一个乱序处理器。 处理器包括用于分配多个负载和多个存储的虚拟加载存储队列，其中可以在处理器的加载存储队列的实际物理大小之外容纳更多的负载和更多存储; 其中所述处理器除了加载和存储之外分配超出所述加载/存储队列的实际物理大小限制的其他指令; 并且其中即使中间加载或存储在加载存储队列中没有空格，也可以调度和执行其他指令。

公开(公告)号：EP1321863A2

公开(公告)日：2003-06-25

申请号：EP02258102.9

申请日：2002-11-25

申请人： Agere Systems Inc.

发明人： Chen, Jian-Guo ,  Clune, David E. ,  Moller, Hanan Z. ,  Sonnier, David P.

IPC分类号： G06F17/30 ,  H04L12/56

CPC分类号： G06F5/10 ,  G06F2205/064 ,  H04L49/25 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9073

摘要： A processing system comprises processing circuitry (102) and memory circuitry (104) coupled to the processing circuitry (102). The memory circuitry (104) is configurable to maintain at least one queue structure representing a list of data units (e.g., pointers to packets stored in a packet memory) (106). The queue structure is partitioned into two or more blocks (e.g., chunks) wherein at least some of the blocks of the queue structure include two or more data units. Further, at least some of the blocks of the queue structure may include a pointer to a next block of the queue structure (e.g., a next chunk pointer). Given such a queue structure, the processing circuitry (102) is configurable to address a first block of the queue structure, and then address a next block of the queue structure by setting the next block pointer of the first block to point to the next block.

摘要翻译： 一种处理系统包括：处理电路（102）和耦合到所述处理电路（102）的存储器电路（104）。 所述存储器电路（104）被配置为保持至少一个队列结构较数据单元（E. G.指针存储在包存储器的数据包）（106）的列表。 队列结构被划分为两个或更多个块（例如，块）worin至少一些队列结构的块包括两个或更多个数据单元。 此外，至少一些所述队列结构的块可以包括一个指针，指向队列结构（E. G.，下一组块指针）的下一个块。 鉴于求队列结构，所述处理电路（102）是可配置的，以解决该队列结构的第一嵌段，和然后通过设置在第一块的下一个块指针地址的队列结构的下一个块，以指向下一个块 ，

公开(公告)号：EP0760501B1

公开(公告)日：2002-02-20

申请号：EP95410092.1

申请日：1995-09-04

申请人： Hewlett-Packard Company, A Delaware Corporation

发明人： Regache, Pascal

IPC分类号： G06F5/06

CPC分类号： G06F5/06 ,  G06F2205/064

公开(公告)号：EP0522224B1

公开(公告)日：1998-10-21

申请号：EP91810548.7

申请日：1991-07-10

申请人： International Business Machines Corporation

发明人： Luijten, Ronald P. ,  Heddes, Marco

IPC分类号： G06F5/06

CPC分类号： G06F5/06 ,  G06F2205/064

公开(公告)号：EP0832457A1

公开(公告)日：1998-04-01

申请号：EP96919329.0

申请日：1996-06-06

申请人： Emulex Corporation

发明人： RICKARD, Wayne ,  FIACCO, Peter ,  CHAU, Vi

IPC分类号： G06F13 ,  G06F5 ,  G06F12 ,  H04L13

CPC分类号： G06F5/06 ,  G06F12/023 ,  G06F2205/064

摘要： A partitioned memory (45) is divided into a number of large buffers (60), and one or more of the large buffers is divided to create an equal number of small buffers (65). Each remaining large buffer is associated with one small buffer, and the paired buffers may be addressed by a single pointer. The pointers are stored in a first-in-first-out unit to create a pool of available buffer pairs.

公开(公告)号：EP0651334A1

公开(公告)日：1995-05-03

申请号：EP94307056.5

申请日：1994-09-27

申请人： International Business Machines Corporation

发明人： Johns, Charles Ray ,  Rahim, Omar Mahmoud ,  Rice, David Andrew ,  Cherichetti, Cory Ansel ,  Dinicola, Paul David ,  Van Nostrand, Mark Ernest

IPC分类号： G06F13/28 ,  G06F5/06

CPC分类号： G06F5/12 ,  G06F5/065 ,  G06F13/28 ,  G06F2205/064 ,  G06F2205/066 ,  G06F2205/126

摘要： Data is transferred from a host system to a subsystem connected to the host by a system bus in an efficient manner using one or more virtual first in first out (FIFO) registers in host memory and a corresponding set of virtual FIFOs located in the subsystem memory. A transmission controller controls the transfer of data from the host FIFOs to the subsystem FIFOs while the subsystem processor reads and processes data from the subsystem FIFO. By accumulating data in the host FIFOs before transfer to the subsystem, overhead associated with starting and stopping data transfers over the system bus is substantially reduced.

摘要翻译： 使用主机存储器中的一个或多个虚拟先进先出（FIFO）寄存器和位于子系统存储器中的对应的一组虚拟FIFO，数据通过系统总线以有效的方式从主机系统传送到连接到主机的子系统 。 传输控制器控制从主机FIFO到子系统FIFO的数据传输，同时子系统处理器从子系统FIFO读取和处理数据。 通过在传送到子系统之前在主机FIFO中累加数据，与系统总线上的数据传输启动和停止相关联的开销显着减少。

公开(公告)号：EP0551191A1

公开(公告)日：1993-07-14

申请号：EP93300076.2

申请日：1993-01-06

申请人： DIGITAL EQUIPMENT CORPORATION

发明人： Chmielecki, Stanley, Jr. ,  Itkowsky, Frank A., Jr. ,  Koning, G Paul ,  Washabaugh, Douglas M ,  Ramakrishnan, Kadangode K

IPC分类号： G06F5/06 ,  G06F13/12

CPC分类号： G06F5/12 ,  G06F13/128 ,  G06F13/24 ,  G06F2205/064 ,  G06F2205/126

摘要： An apparatus and method for transferring data in a data processing system to and from a host system (11). A communication adapter (10) or input/output controller device is provided in which queues (36) are utilized to transfer information between the adapter or controller and the host system (11). In order to minimize the amount of time a system or I/O bus or network is used during transfer of data between the adapter or controller and the host system, and reduce the amount of work that must be performed by the host system (11), the number of interrupts by the adapter (10) or controller of the host system is limited to the minimum amount necessary by using an interrupt arm mechanism (44) and by keeping track of completion indices stored in the host system.

摘要翻译： 用于在数据处理系统和从主机系统（11）传递环数据的装置和方法。 一种通信适配器（10）或输入/输出控制器装置是在其中的队列（36）被用来传输适配器或控制器和主机系统（11）之间的信息提供。 为了最小化的时间的系统或I / O总线或网络适配器或控制器和主机系统之间的数据传送期间使用的量，以及减少的工作量并必须由主机系统执行（11） ，中断通过所述适配器（10）或主机系统的控制器的数量是通过使用必要中断臂机构（44）和通过跟踪存储在主机系统完成索引限于最小量。

公开(公告)号：EP0378195A3

公开(公告)日：1992-03-18

申请号：EP90100444.0

申请日：1990-01-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shobatake, Yasuro ,  Kumaki, Yoshinari

IPC分类号： G06F5/06 ,  G06F13/18

CPC分类号： H04Q11/0478 ,  G06F5/065 ,  G06F13/18 ,  G06F2205/064 ,  G06F2205/066 ,  H04L2012/5651 ,  H04L2012/5681

摘要： A buffer device capable of dealing with multiple priority levels in which the efficiency of the memory capacity utilization can be improved such that the priority levels can be handled at the higher efficiency with smaller memory capacities, and which is adaptable to a high speed buffer implementation. The device includes a data register array (10) containing empty data registers and imaginary FIFO queues, and an administrative register array (11) comprised of a two port RAM (11a,11b) for storing pointer chains specifying the imaginary FIFO queues. The input of data is accompanied by the modification of the pointer chain to extend it, whereas the output of data is accompanied by the modification of the pointer chain to shorten it, so that the imaginary FIFO queues are administered in flexible manner in order to achieve efficient memory capacity utilization. The procedure for controlling the imaginary FIFO queues can be executed in parallel because of the independency of read and write operations in the two port RAM.

公开(公告)号：EP0425764A2

公开(公告)日：1991-05-08

申请号：EP90113707.5

申请日：1990-07-17

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Furuse, Iwato, c/o Computer Seisakusho

IPC分类号： G06F5/06

CPC分类号： G06F5/06 ,  G06F2205/064

摘要： Disclosed is an input data control system having a plurality of buffers for storing input data transmitted from a terminal, and management information storage regions for storing management information on the input data storage regions and the input data stored therein. A data I/O management program permits the corresponding input data storage region to store the data given from the terminal on the basis of the management information stored in the management information storage regions and updates the corresponding management information.

摘要翻译： 公开了一种输入数据控制系统，具有用于存储从终端发送的输入数据的多个缓冲器和用于存储关于输入数据存储区域和存储在其中的输入数据的管理信息的管理信息存储区域。 数据I / O管理程序允许相应的输入数据存储区域根据存储在管理信息存储区域中的管理信息存储从终端给出的数据，并更新相应的管理信息。