公开(公告)号：EP4088181B1

公开(公告)日：2024-06-26

申请号：EP20828443.0

申请日：2020-11-24

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3836 ,  G06F9/3824

公开(公告)号：EP2862089B1

公开(公告)日：2018-12-26

申请号：EP12879101.9

申请日：2012-11-26

Applicant: International Business Machines Corporation

Inventor： GREINER, Dan ,  ROGERS, Robert ,  SITTMANN, Gustav

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F9/30047 ,  G06F9/3824 ,  G06F12/1009 ,  G06F2212/683

Abstract: A first and a second operand are compared. If they are equal, the contents of register R1+1 are stored at the second-operand location, and the specified CPU or CPUs in the configuration are cleared of all TLB table entries of the designated type formed through the use of the replaced entry in storage, and all lower-level TLB table entries formed through the use of the cleared higher-level TLB table entries. A valid DAT table entry is replaced with a new entry, and the Translation Lookaside Buffer (TLB) is purged of any copies of (at least) the single entry on all CPUs in the configuration. If the first and second operands are unequal, the second operand is loaded at the first-operand location. The comparison result is indicated by the condition code. A method, system and a computer program product are provided.

公开(公告)号：EP3055769B1

公开(公告)日：2018-10-31

申请号：EP14891601.8

申请日：2014-12-14

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： COL, Gerard, M. ,  EDDY, Colin ,  HENRY, G., Glenn

IPC: G06F9/38

CPC classification number: G06F9/3855 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/1009

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.

公开(公告)号：EP3032400B1

公开(公告)日：2018-10-31

申请号：EP15196876.5

申请日：2015-11-27

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： COL, Gerard ,  EDDY, Colin ,  HENRY, G. Glenn

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/30043 ,  G06F9/30083 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861 ,  G06F9/3863 ,  G06F13/24 ,  Y02D10/14

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.

公开(公告)号：EP3365769A1

公开(公告)日：2018-08-29

申请号：EP16857989.4

申请日：2016-10-05

Applicant: KnuEdge, Inc.

Inventor： PALMER, Douglas A. ,  WHITE, Andrew

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  G06F9/44 ,  G06F12/08 ,  G06F15/16 ,  G06F15/78

CPC classification number: G06F9/30098 ,  G06F9/3012 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/54 ,  G06F9/544 ,  G06F15/163 ,  G06F15/7825

Abstract: A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.

公开(公告)号：EP2709003B1

公开(公告)日：2018-08-01

申请号：EP11865214.8

申请日：2011-09-15

Applicant: ZTE Corporation

Inventor： LI, Lihuang ,  LI, Wei

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F17/30569 ,  G06F9/30025 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3873 ,  G06F9/3893

Abstract: The disclosure discloses a loopback structure and data loopback processing method of a processor. The loopback structure includes a register file unit, a data storing unit, and a data reading unit; wherein the register file unit is configured to provide a data reading-writing service for the data storing unit and the data reading unit; the data storing unit is connected to the register file unit, and is configured to read data via a reading port of the register file unit, to perform a data transformation on the read data, and to feed the transformed data back to the data reading unit; and the data reading unit is connected to the register file unit and the data storing unit, and is configured to transform the data fed back by the data storing unit, and to write the transformed data in the register file unit via a writing port of the register file unit. With the disclosure, it is possible to increase efficiency of the processor and decrease power consumption of the processor.

公开(公告)号：EP3350719A1

公开(公告)日：2018-07-25

申请号：EP16775383.9

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F15/78 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350707A1

公开(公告)日：2018-07-25

申请号：EP16775377.1

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F12/0806 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350706A1

公开(公告)日：2018-07-25

申请号：EP16775374.8

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F12/0806 ,  G06F9/38

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350688A1

公开(公告)日：2018-07-25

申请号：EP16775905.9

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.