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    NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD OF OPERATION
    12.
    发明公开
    NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD OF OPERATION 审中-实审

    公开(公告)号：EP4339953A1

    公开(公告)日：2024-03-20

    申请号：EP23306442.7

    申请日：2023-08-31

    申请人： STMicroelectronics (ALPS) SAS ,  STMicroelectronics S.r.l.

    发明人： CONTE, Antonino ,  MACCARRONE, Agatino Massimo ,  TOMAIUOLO, Francesco ,  JOUANNEAU, Thomas ,  RUSSO, Vincenzo

    IPC分类号： G11C13/00 ,  G11C16/08 ,  G11C8/08

    摘要： In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles (6) arranged horizontally. Each tile (6) includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder (90) is configured to receive a set of encoded address signals (ADD_LS[1:0], ADD_LY[2:0], ADD_LX[2:0], ADD_PX[3:0]) to produce pre-decoding signals (LS[3:0], LY[7:0], LX[7:0], PX[15:0]). A central row decoder (12) is arranged in line with the plurality of tiles (6), receives the pre-decoding signals and produces level-shifted pull-up (PullUp ) and pull-down (WLD ) driving signals for driving the word lines. First buffer circuits (30) are arranged on a first side of each tile (6). Each of the first buffer circuits (30) is coupled to a respective word line, receives a level-shifted pull-up driving signal (PullUp ) and a level-shifted pull-down driving signal (WLD ), and selectively pulls up or pulls down the respective word line as a function of the values of the received signals. Second buffer circuits (40) are arranged on a second side of each tile (6). Each of the second buffer circuits (40) is coupled to a respective word line, receives a level-shifted pull-down driving signal (WLD ), and selectively pulls down the respective word line as a function of the value of the received signal. The pre-decoding signals are in the voltage range of 0 V to about 0.9 V, and the level-shifted pull-up and pull-down driving signals (PullUp , WLD ) are in the voltage range of 0 V to a tile supply voltage (V XSECTOR ) of the memory sector.

    MEMRISTIVE STRUCTURE AND MEMRISTIVE DEVICE
    15.
    发明公开
    MEMRISTIVE STRUCTURE AND MEMRISTIVE DEVICE 审中-公开

    公开(公告)号：EP4303875A1

    公开(公告)日：2024-01-10

    申请号：EP23183823.6

    申请日：2023-07-06

    申请人： TechIFab GmbH

    发明人： SCHMIDT, Heidemarie ,  DU, Nan ,  SKORUPA, Ilona

    IPC分类号： G11C11/22 ,  G11C13/00 ,  H10B53/30 ,  H10N70/00

    摘要： According to various aspects, a memristive structure (100) is provided including: a first electrode (110), a second electrode (120), and a memristive element (130) arranged between the first electrode and the second electrode; wherein the memristive element (130) includes a memristive material that has a memristive switching capability and a ferroelectric polarization capability, and wherein the memristive material has a crystalline microstructure configured to suppress a ferroelectric switching of the memristive element when memristively switching the memristive element in response to an electric field caused by a voltage drop over the memristive element applied via the first electrode and the second electrode, wherein the crystalline microstructure: includes one or more crystallites having a main polarization direction perpendicular to the electric field, or is a poly-crystalline microstructure with a plurality of crystallites, wherein a spatial orientation of the plurality of crystallites is randomly distributed with respect to the electric field.

    A MOLECULAR SYNTHESIS ARRAY
    16.
    发明公开
    A MOLECULAR SYNTHESIS ARRAY 审中-公开

    公开(公告)号：EP4286042A1

    公开(公告)日：2023-12-06

    申请号：EP22176397.2

    申请日：2022-05-31

    申请人： Imec VZW

    发明人： LOCKHART DE LA ROSA, Cesar Javier

    IPC分类号： B01J19/00 ,  G11C13/00

    摘要： According to an aspect of the present inventive concept there is provided a molecular synthesis array comprising: a substrate; an insulating layer (202) arranged on the substrate; a plurality of column lines (102) extending in parallel along a column direction of the molecular synthesis array (100), and a plurality of row lines (104) extending in parallel along a row direction of the molecular synthesis array (100), wherein the column lines (102) are vertically separated from the row lines (104) and extend transverse to the row lines (104); a plurality of synthesis cells (105), wherein each cell (200) is coupled to a respective pair of a column line and a row line and comprises: a lower electrode (226) and an upper electrode (206) vertically separated from each other and embedded in the insulating layer (202), a synthesis well (223) extending from an upper surface (225) of the insulating layer (202) to the lower electrode (226), through the insulating layer (202) and through the upper electrode (206), wherein the well (223) exposes a surface portion (214) of the upper electrode (206) and a surface portion (220) of the lower electrode (226), and a select transistor (106) having a first terminal (114a), a second terminal (114b) and a gate terminal (114c), the first and second terminals (114a, 114b) forming respective source/drain terminals of the select transistor (106), wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the lower electrode (226), and the upper electrode (206) is coupled to a reference voltage, or wherein the gate terminal (114c) is coupled to the row line, the first terminal (114a) is coupled to the column line, the second terminal (114b) is coupled to the upper electrode (206), and the lower electrode (226) is coupled to a reference voltage.

    MEMORY DATA READING CIRCUIT AND MEMORY
    20.
    发明公开
    MEMORY DATA READING CIRCUIT AND MEMORY 审中-公开

    公开(公告)号：EP4231299A1

    公开(公告)日：2023-08-23

    申请号：EP20961995.6

    申请日：2020-11-20

    申请人： Huawei Technologies Co., Ltd.

    发明人： CAI, Jiangzheng ,  BU, Mingen ,  OUYANG, Sheng

    IPC分类号： G11C13/00

    摘要： A stored data reading circuit and a memory are provided, which relate to the field of integrated circuit technologies, to resolve a problem that data read by the stored data reading circuit is inaccurate. The stored data reading circuit (01) includes a first current mirror (301), a first resistor (303), and a voltage amplifier (40). An input end (a) of the first current mirror (301) is connected to a first data reading end (p) of a memory cell, and an output end (b) of the first current mirror (301) is connected to a ground terminal via the first resistor (303). The first current mirror (301) is configured to: amplify a current output at the first data reading end (p) of the memory cell to a first mirror current (IRO) through mirroring, and output the first mirror current (IRO) to the output end (b) of the first current mirror (301). A first input end (c) of the voltage amplifier (40) is connected to the output end (b) of the first current mirror (301), a second input end (d) of the voltage amplifier (40) is configured to receive a reference voltage (Iref), and an output end (e) of the voltage amplifier (40) is connected to an output end of the stored data reading circuit (01).