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公开(公告)号：EP4339953A1
公开(公告)日：2024-03-20
申请号：EP23306442.7
申请日：2023-08-31
发明人： CONTE, Antonino , MACCARRONE, Agatino Massimo , TOMAIUOLO, Francesco , JOUANNEAU, Thomas , RUSSO, Vincenzo
摘要： In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles (6) arranged horizontally. Each tile (6) includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder (90) is configured to receive a set of encoded address signals (ADD_LS[1:0], ADD_LY[2:0], ADD_LX[2:0], ADD_PX[3:0]) to produce pre-decoding signals (LS[3:0], LY[7:0], LX[7:0], PX[15:0]). A central row decoder (12) is arranged in line with the plurality of tiles (6), receives the pre-decoding signals and produces level-shifted pull-up (PullUp ) and pull-down (WLD ) driving signals for driving the word lines. First buffer circuits (30) are arranged on a first side of each tile (6). Each of the first buffer circuits (30) is coupled to a respective word line, receives a level-shifted pull-up driving signal (PullUp ) and a level-shifted pull-down driving signal (WLD ), and selectively pulls up or pulls down the respective word line as a function of the values of the received signals. Second buffer circuits (40) are arranged on a second side of each tile (6). Each of the second buffer circuits (40) is coupled to a respective word line, receives a level-shifted pull-down driving signal (WLD ), and selectively pulls down the respective word line as a function of the value of the received signal. The pre-decoding signals are in the voltage range of 0 V to about 0.9 V, and the level-shifted pull-up and pull-down driving signals (PullUp , WLD ) are in the voltage range of 0 V to a tile supply voltage (V XSECTOR ) of the memory sector.
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公开(公告)号：EP4174859A1
公开(公告)日：2023-05-03
申请号：EP22192488.9
申请日：2022-08-26
发明人： RUTA, Marco , CONTE, Antonino , PISASALE, Michelangelo , MACCARRONE, Agatino Massimo , TOMAIUOLO, Francesco
摘要： A low-dropout voltage regulator circuit (40) is disclosed. The regulator receives an input voltage ( Vcc ) at an input node (400) and produces a regulated output voltage ( V REG ) at an output node (402). A first feedback network (R1, 412, 414) produces a feedback signal ( VFB ) indicative of the output voltage ( V REG ), and compares the feedback signal to a reference signal ( VREF ) to assert and de-assert a first pulsed control signal ( COMP_OU-T ) when the reference signal is higher and lower, respectively, than the feedback signal. A time-averaged value of the first pulsed control signal is a function of the difference between the reference signal and the feedback signal. A second feedback network (R2, 418, 420) produces a threshold signal ( VTH ) indicative of the input voltage, and compares the output voltage ( V REG ) to the threshold signal to assert and de-assert a second control signal ( VCC_EN ) when the threshold signal is higher and lower, respectively, than the output voltage. A charge pump circuit (408) is enabled ( PMP_EN ) if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage ( V BL_ S UPPLY ) higher than the input voltage ( Vcc ) . A first pass element (404a) arranged between the input node and the output node is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element (404b) arranged between the charge pump (408) and the output node (402) is selectively activated when the second control signal is de-asserted.
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3.发明公开
公开(公告)号：EP4123651A1
公开(公告)日：2023-01-25
申请号：EP22181479.1
申请日：2022-06-28
发明人： MACCARRONE, Agatino Massimo , CONTE, Antonino , TOMAIUOLO, Francesco , PISASALE, Michelangelo , RUTA, Marco
IPC分类号： G11C13/00
摘要： A circuit comprises a plurality of memory cells (C1, ..., CN). Each memory cell in the plurality of memory cells (C1, ..., CN) includes a phase-change memory storage element (E1) coupled in series with a respective current-modulating transistor (PH1) between a supply voltage node (V SUPPLY ) and a reference voltage node. The current-modulating transistors (PH1) are configured to receive a drive signal (DRV _GATE) at a control terminal thereof and to inject respective programming currents (I CELL ) into the respective phase-change memory storage elements (E1) as a function of the drive signal (DRV_GATE). A driver circuit (32) is configured to produce the drive signal (DRV _GATE) at a common control node (N C ), and the common control node (N C ) is coupled to the control terminals of the current-modulating transistors (PH1) in the plurality of memory cells (C1, ..., CN). The drive signal (DRV _GATE) modulates the programming currents (I CELL ) to produce set programming current pulses and reset programming current pulses. A current generator circuit (80) is configured to inject a compensation current (I DRV_GATE ) into the common control node (N C ) in response to the current-modulating transistors (PH1) injecting the programming currents (I CELL ) into the respective phase-change memory storage elements (E1).
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