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    Method and system for implementing a reduced latency, wideband pulse density modulation digital to analog converter
    11.
    发明公开
    Method and system for implementing a reduced latency, wideband pulse density modulation digital to analog converter 有权
    方法和系统，用于实现宽带脉冲密度调制的数字 - 模拟转换器具有降低的延迟

    公开(公告)号：EP1793501A1

    公开(公告)日：2007-06-06

    申请号：EP06125060.1

    申请日：2006-11-30

    申请人： HONEYWELL INC.

    发明人： DuPuis, Paul B ,  Dickey, John A.

    IPC分类号： H03M7/00 ,  H03M5/04

    CPC分类号： H03M7/3028 ,  H03M1/48 ,  H03M7/3031

    摘要： According to one aspect of the present invention, this invention implements a low latency, wide bandwidth method and system for converting numeric digital values into pulse density modulated analog output signals. Such output signals having their lowest output frequency much closer to the system clock frequency, thus enabling wider bandwidth and simpler implementations than with traditional approaches. This method is based in part on an adaptation of Bresenham's Line Drawing Algorithm.

    摘要翻译： 。根据本发明的一个方面中，本发明实现了一种低等待时间，高带宽的方法和系统用于将数字数值成脉冲密度调制模拟输出信号。 具有最低的输出频率更接近系统时钟频率，从而实现抗蚀剂THUS带宽和比用传统的实现途径简单搜索输出信号。 该方法是基于对在布氏线算法的适应一部分。

    Decoding chip streams
    12.
    发明公开
    Decoding chip streams 失效
    Chipströmedekodierung

    公开(公告)号：EP0973264A1

    公开(公告)日：2000-01-19

    申请号：EP98305567.4

    申请日：1998-07-13

    申请人： Hewlett-Packard Company

    发明人： Beale, Martin Warwick

    IPC分类号： H03M5/04 ,  H04B1/707

    CPC分类号： H04L7/0334 ,  H04B1/707

    摘要： A method and apparatus are described for decoding a stream of data which has been encoded into a chip stream so that a chip rate and phase of the chip stream can be derived from the encoded data.
    The method comprises the steps of: generating a clock signal (clk) having a clock rate which is approximately equal to the chip rate or an integer multiple thereof; passing the chip stream along a multi-stage delay line (14); for each clock cycle, sampling data of the chip stream at a plurality of the stages of the delay line to produce a set of oversamples ( oversamples ); for each clock cycle, producing an estimate ( edgepos ) of a position in a respective set of the oversamples of a chip edge in the chip stream; for at least some of the clock cycles, selecting at least one of the oversamples ( dec_chip(0), dec_chip(1)) having a position within a confined range with respect to the estimated chip edge position; and outputting the selected oversamples.
    The method obviates the need for a high frequency oversampling clock or a variable frequency clock. The delay per stage of the delay line does not need to be stabilised if a calibration method is employed periodically between reception sessions.

    摘要翻译： 描述了一种用于对已经被编码为码片流的数据流进行解码以便可以从编码数据导出码片流的码片速率和相位的方法和装置。 该方法包括以下步骤：产生具有近似等于码片速率或其整数倍的时钟速率的时钟信号（clk）; 沿着多级延迟线（14）通过芯片流; 对于每个时钟周期，在延迟线的多个级的芯片流的采样数据产生一组过采样（过采样）; 对于每个时钟周期，产生在芯片流中的芯片边缘的相​​应的一组过采样中的位置的估计（edgepos）; 对于至少一些时钟周期，选择具有相对于估计的芯片边缘位置的限制范围内的位置的过采样（dec_chip（0），dec_chip（1））中的至少一个; 并输出所选择的过采样。 该方法避免了对高频过采样时钟或可变频率时钟的需要。 如果在接收会话之间周期性地使用校准方法，则延迟线的每个阶段的延迟不需要稳定。

    SINGLE-CHANNEL COMMUNICATION ENCODING METHOD AND DECODING METHOD, ENCODING CIRCUIT, AND DECODING CIRCUIT
    14.
    发明公开
    SINGLE-CHANNEL COMMUNICATION ENCODING METHOD AND DECODING METHOD, ENCODING CIRCUIT, AND DECODING CIRCUIT 审中-公开

    公开(公告)号：EP4333336A1

    公开(公告)日：2024-03-06

    申请号：EP22879785.8

    申请日：2022-03-15

    申请人： Suzhou Novosense Microelectronics Co., Ltd.

    发明人： HUANG, Jiageng ,  SHENG, Yun ,  LIN, Jianfeng

    IPC分类号： H04L1/00 ,  H03M5/04

    摘要： The present invention relates to an encoding method, a decoding method, an encoding circuit and a decoding circuit for single-channel communication. The encoding method for single-channel communication includes: combining a clock signal and a data signal to a long- and short-code signal, wherein the long- and short-code signal includes a long-code signal and a short-code signal, a pulse width of the long-code signal is consistent with that of the clock signal, and a pulse width of the short-code signal is consistent with that of the clock signal; and the long-code signal and the short-code signal have different duty cycles. According to the encoding method, the clock signal and the data signal are encoded at the same time, which can reduce the circuit complexity and thus the wire bonding for chip packaging.

    COMMUNICATION DEVICE, ENDOSCOPE DEVICE AND COMMUNICATION METHOD
    17.
    发明公开
    COMMUNICATION DEVICE, ENDOSCOPE DEVICE AND COMMUNICATION METHOD 有权
    通信设备，内窥镜设备和通信方法

    公开(公告)号：EP2665232A1

    公开(公告)日：2013-11-20

    申请号：EP12774583.4

    申请日：2012-04-05

    申请人： Olympus Medical Systems Corp.

    发明人： TANABE Takahiro ,  KAWATA Susumu

    IPC分类号： H04L25/49 ,  A61B1/04 ,  H03M5/04

    CPC分类号： A61B1/00002 ,  A61B1/00006 ,  A61B1/00009 ,  A61B1/00011 ,  H04L25/4915

    摘要： A communication device has a transmission device 17 and a reception device 19. The transmission device 17 calculates a DC balance value of input data, compares the DC balance value and a cumulative value thereof, and compares the sign of the DC balance value and the sign of the cumulative value. When the signs are the same sign, the transmission device generates intermediate data by exchanging a first value and a second value with each other for all the bits of the input data, and generates predetermined information indicating that all the bits have been inverted. When the signs are different signs, the transmission device performs a process of setting the input data as the intermediate data and transmits the intermediate data by a serial signal. The reception device 19 generates output data by exchanging the first value and the second value with each other for all the bits of the received data when the predetermined information is generated, and sets the received data which is received as the output data when the predetermined information is not generated.

    摘要翻译： 通信设备具有发送设备17和接收设备19.发送设备17计算输入数据的DC平衡值，比较DC平衡值及其累积值，并将DC平衡值的符号与符号 的累计值。 当符号是相同符号时，传输设备通过相互交换输入数据的所有比特的第一值和第二值来产生中间数据，并且产生指示所有比特已被反转的预定信息。 当符号是不同符号时，传输设备执行将输入数据设置为中间数据并且通过串行信号传输中间数据的处理。 接收装置19在生成了规定的信息的情况下，对接收数据的全部比特相互交换第一值和第二值，生成输出数据，在规定的信息的情况下，将接收到的接收数据作为输出数据进行设定 没有生成。

    Data communication between capacitive isolated voltage domains
    18.
    发明公开
    Data communication between capacitive isolated voltage domains 有权
    电容性隔离电压域之间的数据通信

    公开(公告)号：EP2658196A1

    公开(公告)日：2013-10-30

    申请号：EP13158121.7

    申请日：2013-03-07

    申请人： NXP B.V.

    发明人： Boezen, Hendrik ,  Bredius, Martijn

    IPC分类号： H04L25/02 ,  H04B5/00 ,  H04B14/02 ,  H03M5/04 ,  H03M5/08

    CPC分类号： H03M5/04 ,  H03M5/08 ,  H04B5/0012 ,  H04B14/026 ,  H04L25/0266

    摘要： In one embodiment, a method of communicating data values over a three conductor interface is provided. Different data values are transmitted by generating and transmitting three respective signals to a receiver using three conductors. The first signal is maintained as a set voltage level. The second signal is alternated between a high voltage and a low voltage according to a carrier frequency. The third signal is alternated between the high and low voltages and is out of phased with the second signal. To transmit a first data value, the first signal is generated on a first conductor, the second signal is generated on a second conductor, and the third signal is generated on a third conductor. To transmit a second data value, the second signal is generated on the first conductor, the first signal is generated on the second conductor, and the third signal is generated on the third conductor.

    摘要翻译： 在一个实施例中，提供了通过三导体接口传送数据值的方法。 通过使用三个导体产生三个相应的信号并将其发送到接收器来发送不同的数据值。 第一个信号保持为设定的电压电平。 第二信号根据载波频率在高电压和低电压之间交替。 第三信号在高电压和低电压之间交替并且与第二信号相位不同。 为了发送第一数据值，在第一导体上生成第一信号，在第二导体上生成第二信号，并且在第三导体上生成第三信号。 为了发送第二数据值，在第一导体上生成第二信号，在第二导体上生成第一信号，并且在第三导体上生成第三信号。