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公开(公告)号：EP0272800A3
公开(公告)日：1990-03-28
申请号：EP87310286.7
申请日：1987-11-20
IPC分类号： H04M19/00
CPC分类号： H04M19/005
摘要： A typical active impedance line feed circuit includes tip and ring amplifiers (20, 40) being controlled in response to signals at tip and ring voltage taps (6, 7) by a control circuit (60) to exhibit a.c. impedance and d.c. resistance characteristics for the purpose of supplying energizing current via tip and ring terminals (2, 3) for tip and ring leads of two wire communication line. In one example of the active impedance line feed circuit, improved operational tolerance of longitudinal interference and of a ground fault condition is provided by a d.c. amplifier (210a) being responsive to voltages at the tip and ring terminals. The circuit is characterized in that an inverting input of the d.c. amplifier is connected via resistors (212a, 313a) to the tip and ring voltage taps. In operation, the d.c. amplifier provides complete cancellation of all common mode signals at the tip and ring voltage taps. A compensation amplifier (235) is also connected between the tip and ring voltage taps and is responsive to the output of a control amplifier (231) for compensating for non-symmetrical current, the non-symmetrical current being introduced between the tip and the ring voltage taps by normal operation of the control circuit. Thereby, a threshold of ground fault current limiting action is substantially constant under all operating conditions. The d.c. amplifier is conveniently manufacturable in integrated circuit technology along with the remaining amplifiers in the active impedance line feed circuit.
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公开(公告)号：EP0239216A3
公开(公告)日：1990-03-14
申请号：EP87301212.4
申请日：1987-02-12
IPC分类号： H01L27/08 , H01L29/72 , H01L21/285
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/0804 , Y10S148/123 , Y10S148/124
摘要： A process for fabricating a CMOS compatible bipolar transistor is described. The transistor, which is of the polysilicon emitter type, is fabricated by forming a p-type layer in a well, providing a polysilicon emitter in contact with the layer, using the emitter as a mask to implant p⁺-type base contact regions, and applying contacts to the device.
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公开(公告)号：EP0250075A3
公开(公告)日：1990-02-14
申请号：EP87303804.6
申请日：1987-04-29
发明人： Kun, Randall Douglas
CPC分类号： H04Q11/0428
摘要： In an integrated services digital network (ISDN) a telephone subscriber is physically connected to a telephone exchange by a digital signal subscriber loop which provides in time division multiplex (TDM), two B channels and a D channel. The two B channels are used for voice and data at a bit rate of sixty-four kilobits per second each. The D channel is used for packet data and for telephone signalling and supervision at a bit rate of sixteen kilobits per second. An ISDN D channel handler, in an exchange termination (ET) collects D channel data from and distributes D channel data to various ISDN subscriber lines. A frame processor, in the D channel handler, receives D channel information as it occurs in each of the receive channels. It directs D channel data to a receive buffer storage location where it is accessible by a translator. The translator recognizes information in the data which relates to supervisory and signalling functions, and passes the information to a central controller in the ET. Likewise, signalling and supervisory information destined for an ISDN subscriber line is translated into ISDN compatible data which is stored in transmit buffer storage locations. The frame processor subsequently pulls this data from the storage locations, and formats it according to CCITT standard, before transmitting it on the appropriate transmit D channel of the TDM bit stream to the subscriber. Packet data received in the D channel is recognized after is has been stored in the receive buffer storage location and then is immediately queued for transmission via the frame processor and a digital transmission link to a separate packet network. Packet data from the separate packet network is received from the digital transmission link and stored via the frame processor in buffer storage locations. Subsequently, the information bits of each stored data packet are formatted according to the CCITT standard by the frame processor, and transmitted to the intended subscriber on the appropriate D channel.
摘要翻译： 在综合业务数字网（ISDN）中，电话用户通过数字信号用户环路物理地连接到电话交换机，数字信号用户环路提供时分复用（TDM），两个B信道和D信道。 两个B通道以每秒64位千比特的比特率用于语音和数据。 D信道用于分组数据和电话信令和监视，速率为每秒十六千比特。 在交换终端（ET）中的ISDN D信道处理器收集D信道数据并将D信道数据分发给各种ISDN用户线路。 在D信道处理器中的帧处理器接收在每个接收信道中出现的D信道信息。 它将D通道数据指向可由翻译器访问的接收缓冲存储位置。 翻译器识别与监控和信号功能相关的数据中的信息，并将信息传递给ET中的中央控制器。 同样，发往ISDN用户线路的信令和监控信息被转换成存储在发送缓冲存储位置的ISDN兼容数据。 帧处理器随后从存储位置拉出该数据，并根据CCITT标准对其进行格式化，然后在TDM比特流的适当的发送D信道上向用户发送该数据。 在D信道中接收的分组数据在已经存储在接收缓冲器存储位置中之后被识别，然后被立即排队等待经由帧处理器传输，并且将数字传输轻易地分配到单独的分组网络。 从数字传输链路接收来自分离分组网络的分组数据，并经由帧处理器在缓冲器存储位置中存储。 随后，每个存储的数据分组的信息比特根据帧处理器根据CCITT标准进行格式化，并在合适的D信道上发送给预期用户。
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公开(公告)号：EP0252630A3
公开(公告)日：1989-11-15
申请号：EP87305415.9
申请日：1987-06-18
发明人： Grover, Wayne Davy
IPC分类号： H04J3/07
摘要： In a high-speed fiber-optic tranmission system, data streams are synchronized using fixed stuffing before being multiplexed for transmission. The fixed stuffing information is replaced with forward error correction (FEC) information, whereby FEC is effected without any increase in transmission speed. FEC information blocks of each data stream can be synchronized to the frame timing of the transmission system, or they can be relatively unsynchronized. In the latter case, an FEC decoder acts in a self-framing manner to synchronize itself to the FEC information blocks of the respective data stream.
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公开(公告)号：EP0230714A3
公开(公告)日：1989-10-11
申请号：EP86307751.7
申请日：1986-10-08
IPC分类号： H03M5/18
CPC分类号： H04L25/4908
摘要： The system uses a 3B2T line code, i.e. one in which sets of three or triplets of binary digits are converted into pairs or duplets of ternary elements. All nine of the possible ternary duplets are used, in such a way that the same ternary duplet does not occur twice consecutively. This is done in one version by using the ninth duplet 00 as a repeat indicator, and in the other version by a conversion process in which each conversion operation takes into account the result of the preceding operation.
摘要翻译： 该系统使用3B2T线代码，即其中一组三位或三位二进制数字被转换成三元组的成对或双倍的代码。 所有九种可能的三元小片都是这样使用的，即相同的三元小片不会连续出现两次。 这是通过使用第九小区00作为重复指示符在一个版本中完成的，并且在另一个版本中通过其中每个转换操作考虑前述操作的结果的转换过程来完成。
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238.发明授权Active impedance transformer-assisted line feed circuit with filtering function of supervision signals 失效主动阻抗变压器辅助线路馈线与监控信号的过滤功能
公开(公告)号：EP0199865B1
公开(公告)日：1989-10-11
申请号：EP85303095.5
申请日：1985-05-01
IPC分类号： H04M19/02
CPC分类号： H04M3/2272 , H04M19/005 , H04M19/026
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239.发明公开Monolithic integration of optoelectronic and electronic devices 失效Monolithische集成von optoelektronischen und elektronischen Bauelementen。
公开(公告)号：EP0335491A2
公开(公告)日：1989-10-04
申请号：EP89301508.1
申请日：1989-02-16
发明人： Mand, Ranjit Singh
CPC分类号： H01L21/8252 , H01L27/15
摘要： In the monolithic integration of HFET and DOES devices, a wide band gap carrier confining semiconductor layer is provided only at predetermined locations where DOES devices are desired. This layer is not provided at other predetermined locations where HFET devices are desired as it would constitute a shunt path which would degrade the high frequency operation of the HFET devices. The invention is particularly useful where monolithic integration of optical sources, optical detectors, and electronic amplifying or switching elements is desired.
摘要翻译： 在HFET和DOES器件的单片集成中，仅在需要DOES器件的预定位置处提供宽带隙载流子限制半导体层。 该层不设置在需要HFET器件的其它预定位置处，因为它将构成将降低HFET器件的高频工作的并联路径。 本发明在需要光源，光学检测器和电子放大或开关元件的单片集成时特别有用。
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240.发明公开Robust, collateral messaging and recovery system and method within a digital switch 失效数字开关中的稳健，收敛消声和恢复系统及方法
公开(公告)号：EP0311347A3
公开(公告)日：1989-10-04
申请号：EP88309227.2
申请日：1988-10-04
发明人： Leuty, Stephen C.
CPC分类号： H04Q11/0407
摘要： System and method are disclosed for collateral out-of-band messaging within the distributed data processing environment in a digital switch which has mainstream in-band data channels. The system comprises independent reset modules, which decode and recognize the out-of-band messages to effect emergency control functions of the distributed processors, such as resetting and jamming an insane processor.
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