公开(公告)号：EP0751558A1

公开(公告)日：1997-01-02

申请号：EP96109954.6

申请日：1996-06-20

申请人： MOTOROLA SEMICONDUCTEURS S.A.

发明人： Foerstner, Jürgen ,  Combes, Myriam ,  Marty-Blavier, Arlette ,  Hautekiet, Guy

IPC分类号： H01L21/74 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L21/74 ,  Y10S148/009

摘要： A method of manufacturing an integrated circuit having a buried layer of a low doped type of conductivity (2) and a buried layer of a highly doped type of the same conductivity (3) by masking a substrate (1) so as to define open areas on the substrate where it is desired to provide the two buried layers and doping the open areas of the substrate with a low concentration of dopants to form the low doped type of buried layer (2) is formed. Then one open area where the low doped type of buried layer (2) is formed is masked and the other open area is doped with a high concentration of dopants to form the highly doped type of buried layer (3).

摘要翻译： 一种通过掩蔽衬底（1）制造具有低掺杂型导电性掩埋层（2）和高掺杂型相同导电性（3）的掩埋层的集成电路的方法，以限定开放区域 在需要提供两个掩埋层的衬底上，并且形成具有低浓度掺杂剂以形成低掺杂型掩埋层（2）的衬底的开放区域。 然后，对形成有低掺杂型掩埋层（2）的一个开放区域进行掩模，另一个开放区域掺杂高浓度的掺杂剂，形成高掺杂型掩埋层（3）。

公开(公告)号：EP0750393A2

公开(公告)日：1996-12-27

申请号：EP96109970.2

申请日：1996-06-20

申请人： MOTOROLA, INC.

发明人： Huynh Luong, Thien ,  Lehning, Heinz

IPC分类号： H03F3/42 ,  H03F3/30

CPC分类号： H03F3/3001 ,  H03F3/42 ,  H03F3/423

摘要： A current sourcing output stage for a high voltage operational amplifier receives a low voltage input signal (V IN ) and provides a high current output signal corresponding to the low voltage input signal at an output terminal (8). A first PNP transistor (Q1) is coupled between a voltage supply (V CC ) and a plurality of cascaded PNP transistors (Q2, Q3, Q8 - Q11) coupled to the output terminal (8). The base of the first PNP transistor (Q1) is coupled to receive the input signal (V IN ) and the bases of the cascaded PNP transistors are coupled to receive different bias voltages A control circuit (Q5 - Q7, R1 - R5) is coupled to the voltage supply (V CC ) and has an input coupled to the output terminal (8) for deriving a plurality of bias voltages and to the cascaded PNP transistors (Q2, Q3, Q8 - Q11) to supply the bias voltages to the respective bases of the cascaded PNP transistors, so that the cascaded PNP transistors (Q2, Q3, Q8 - Q11) are biased by bias voltages dependent on the voltage swing of the output signal.

摘要翻译： 用于高电压运算放大器的电流源输出级接收低电压输入信号（VIN），并在输出端（8）提供对应于低电压输入信号的高电流输出信号。 第一PNP晶体管（Q1）耦合在电压源（VCC）和耦合到输出端子（8）的多个级联PNP晶体管（Q2，Q3，Q8-Q11）之间。 第一PNP晶体管（Q1）的基极被耦合以接收输入信号（VIN），并且级联PNP晶体管的基极被耦合以接收不同的偏置电压。控制电路（Q5-Q7，R1-R5）耦合到 电压源（VCC），并且具有耦合到输出端子（8）的输出，用于导出多个偏置电压和级联PNP晶体管（Q2，Q3，Q8-Q11）以将偏置电压提供给 级联PNP晶体管，使得级联PNP晶体管（Q2，Q3，Q8-Q11）由取决于输出信号的电压摆幅的偏置电压偏置。

公开(公告)号：EP0750316A2

公开(公告)日：1996-12-27

申请号：EP96109958.7

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  Page, Andrew ,  King, Barry ,  Golding, Paul

IPC分类号： G11C19/00

CPC分类号： G06F9/30032 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/583 ,  G11C19/00 ,  H04L9/0662 ,  H04L2209/04 ,  H04L2209/12

摘要： A feedback and shift unit is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a particular operating function, such as a linear feedback shift or a stepping function used by encryption algorithms. The feedback and shift unit (50) comprises a linear feedback shift register (52) for storing a value of the feedback and shift unit. A tap register (56) stores a tap position indicator indicative of tap positions for the feedback and shift unit (50). An input provides data to the feedback and shift unit. A feedback matrix, coupled to receive the data from the input, provides data bits, generated in response to the data and the tap position indicator, that are shifted into the linear feedback shift register (52) to form the value stored therein.

摘要翻译： 布置反馈和移位单元以将处理器（例如DSP）中所需的处理步骤的数量减至最少，以实现特定的操作功能，例如由加密算法使用的线性反馈移位或步进功能。 反馈和移位单元（50）包括用于存储反馈和移位单元的值的线性反馈移位寄存器（52）。 抽头寄存器（56）存储指示反馈和移位单元（50）的抽头位置的抽头位置指示器。 一个输入提供反馈和移位单元的数据。 耦合以从输入接收数据的反馈矩阵提供响应于数据和抽头位置指示符产生的数据位，其被移入线性反馈移位寄存器（52）以形成其中存储的值。

公开(公告)号：EP0749199A1

公开(公告)日：1996-12-18

申请号：EP96108602.2

申请日：1996-05-30

申请人： MOTOROLA SEMICONDUCTEURS S.A.

发明人： L'Hermite, Francois ,  Pauk, Ondrej

IPC分类号： H02M3/335 ,  H04N5/63

CPC分类号： H04N5/63 ,  H02M3/33507 ,  H02M2001/0032 ,  H02M2001/009 ,  Y02B70/16

摘要： A power supply for an electric appliance having an operating mode and a standby mode includes a transformer block (9) for producing a constant power output into two low voltage outputs (Vc and Vcc), an operating power supply circuit (2) coupled to one of the two low voltage outputs (Vcc) to power the appliance during the operating mode, and a receiver circuit (3) coupled to the other low voltage output via an impedance path (14, 15). The receiver circuit (3) includes a switch (17) for switching a very low impedance into a path parallel with the first impedance when it receives a signal indicating that the appliance is to enter the standby mode, so that the voltage at the other low voltage output (Vcc) is reduced, thereby increasing the current drawn by the receiver circuit (3) and thus reducing the power available to the operating power supply circuit (2).

摘要翻译： 具有操作模式和待机模式的电器的电源包括用于产生输出到两个低电压输出（Vc和Vcc）的恒定功率的变压器块（9），耦合到一个的工作电源电路（2） 的两个低电压输出（Vcc）以在操作模式期间为器具供电;以及接收器电路（3），其经由阻抗路径（14,15）耦合到另一低电压输出。 接收器电路（3）包括开关（17），用于在接收到指示器具进入待机模式的信号时将非常低的阻抗切换成与第一阻抗平行的通路，使得另一低电平 电压输出（Vcc）减小，从而增加由接收器电路（3）吸收的电流，从而降低可用于工作电源电路（2）的功率。

公开(公告)号：EP0741406A2

公开(公告)日：1996-11-06

申请号：EP96106731.1

申请日：1996-04-29

申请人： MOTOROLA, INC.

发明人： Bukhman, Yefim ,  Keller, Edward M.

IPC分类号： H01L21/3065

CPC分类号： H01L21/3065

摘要： A scaleable laser and control unit (58) is used to differentially heat portions of a semiconductor substrate (40) during downstream etching. Such differential heating provides a differential etch rate for each portion heated resulting in improved uniformity and reduced etch induced surface damage. An etching chamber (50) capable of containing the downstream plasma and providing a direct line of sight between the substrate (40) and the scanable laser unit (58) is provided. In addition, the system provides for dynamic updating of the process by in situ etch rate and temperature measurements.

摘要翻译： 在下游蚀刻期间，使用可扩展的激光和控制单元（58）来差别地加热半导体衬底（40）的部分。 这种差分加热为加热的每个部分提供差别蚀刻速率，导致改进的均匀性和减少的蚀刻诱发的表面损伤。 提供能够容纳下游等离子体并在基板（40）和可扫描激光单元（58）之间提供直接视线的蚀刻室（50）。 此外，该系统通过原位蚀刻速率和温度测量提供了对过程的动态更新。

公开(公告)号：EP0735669A2

公开(公告)日：1996-10-02

申请号：EP96102657.2

申请日：1996-02-22

申请人： MOTOROLA, INC.

发明人： Koifman, Vladimir ,  Afek, Yachin ,  Kashat, Israel

IPC分类号： H03F3/45

CPC分类号： H03F3/005 ,  H03F3/45479

摘要： A switched capacitor differential circuit switches first and second differential input signals (Vinp1, Vinp2) to respective inputs (A, B) of an operational amplifier (12) via respective first and second signal paths. Each signal path includes a coupling capacitor (13, 14) and two switching devices (2, 3 and 4, 5) to switch the input signals to charge the capacitors at a first phase of a clock signal and to discharge the capacitors onto the inputs of the amplifier at a second phase of the clock signal. In order to remove common mode spikes from transferring to the amplifier, a pair of comon mode capacitors (16, 17) are coupled between the inputs and a common node (15), which is coupled via a pair of switches (6, 7) to the first and second signal paths between the capacitors and the second of the switching devices so that the coupling capacitors are discharged relative to the common node.

摘要翻译： 开关电容差分电路经由相应的第一和第二信号路径将第一和第二差分输入信号（Vinp1，Vinp2）切换到运算放大器（12）的相应输入（A，B）。 每个信号路径包括耦合电容器（13,14）和两个开关器件（2,3和4,5），用于切换输入信号以在时钟信号的第一相位对电容器充电，并将电容器放电到输入端 的时钟信号的第二相位。 为了去除共模模式尖峰传输到放大器，一对共模模式电容器（16,17）耦合在输入端和公共节点（15）之间，该公共节点通过一对开关（6,7）耦合， 到电容器和第二开关器件之间的第一和第二信号路径，使得耦合电容器相对于公共节点放电。

公开(公告)号：EP0735595A2

公开(公告)日：1996-10-02

申请号：EP96103290.1

申请日：1996-03-04

申请人： MOTOROLA, INC.

发明人： Sakamoto, Kurt K. ,  Tracht, Neil T. ,  Pryor, Robert A.

IPC分类号： H01L29/92

CPC分类号： H01L28/40

摘要： A capacitor (58) for an integrated circuit having a conductive trench (50), disposed below a bottom electrode layer (52), that electrically connects the bottom electrode layer to a semiconductor substrate (14, 16). The conductive trench eliminates the need for a top-side contact to the bottom electrode layer. The semiconductor substrate is, for example, connected to ground.

摘要翻译： 一种用于集成电路的电容器（58），其具有设置在底部电极层（52）下方的导电沟槽（50），其将底部电极层电连接到半导体衬底（14,16）。 导电沟槽消除了对底部电极层的顶侧接触的需要。 半导体衬底例如与地连接。

公开(公告)号：EP0733906A1

公开(公告)日：1996-09-25

申请号：EP96103287.7

申请日：1996-03-04

申请人： MOTOROLA, INC.

发明人： Adams, Vistor J. ,  Dougherty, David J.

IPC分类号： G01P1/02

CPC分类号： G01P1/023 ,  H05K3/306 ,  H05K3/308 ,  Y10T29/49121

摘要： A method of forming a package assembly (10) including a package (12) that encapsulates an electronic die. A leadframe (30) has edge rails (32), and the die is disposed on the leadframe. The package is formed around the die to encapsulate it, and the leadframe is trimmed to provide a plurality of leads (14) protruding from a first side of the package. This trimming also provides a support (16) connected to a second side of the package. The support is bent to be substantially orthogonal to the common plane containing the leads. A mounting tip (26) on the support is thus disposed outside of the common plane. This support improves the rigidity and natural bending frequency of the package assembly.

摘要翻译： 形成包括封装（12）的包装组件（10）的方法，做在封装了电子。 的引线框架（30）具有边缘轨道（32），以及管芯设置在引线框架上。 该封装周围所形成的封装它，和引线框架被修整，以提供引线从封装的第一侧突出有多个（14）。 因此，这提供了修整连接到封装的第二侧上的支撑件（16）。 支持弯曲大致正交于包含引线同一平面上。 在支架上的安装顶端（26）是共同平面的外面这样设置。 此支持改善包装组件的刚性，自然弯曲频率。

公开(公告)号：EP0726656A1

公开(公告)日：1996-08-14

申请号：EP96101616.9

申请日：1996-02-05

申请人： MOTOROLA, INC.

发明人： Koifman, Vladimir ,  Afek, Yachin ,  Liberman, Sergio

IPC分类号： H03M3/02 ,  H03M7/00

CPC分类号： H03M7/3022 ,  H03M3/504

摘要： A noise cancelling circuit (1) is used with a D/A converter , the converter including a first modulator (11) and a data output. The circuit (1) comprises an error measuring arrangement (12, 13, 14) for measuring a quantization error signal of the modulator (11). A filter (19) receives the error signal and provides a filtered error signal. A filter compensator (17) coupled to the data output provides a compensated output. A scaler (15) coupled to receive the filtered error signal provides a scaled filtered error signal. A second modulator (16) coupled to receive the scaled filtered error signal provides a single bit stream of error data. A summing arrangement (18) sums the single bit stream of error data and the compensated output from the first modulator and provides a corrected output, such that the error signal is filtered, scaled and modulated and the data output is compensated such that the corrected output is obtained having a substantially reduced quantization error.

摘要翻译： 噪声消除电路（1）与D / A转换器一起使用，转换器包括第一调制器（11）和数据输出。 电路（1）包括用于测量调制器（11）的量化误差信号的误差测量装置（12,13,14）。 滤波器（19）接收误差信号并提供滤波后的误差信号。 耦合到数据输出的滤波器补偿器（17）提供补偿输出。 耦合以接收经滤波的误差信号的缩放器（15）提供缩放滤波的误差信号。 耦合以接收缩放滤波的误差信号的第二调制器（16）提供错误数据的单个比特流。 求和装置（18）将错误数据的单个比特流和来自第一调制器的补偿输出相加并提供校正输出，使得误差信号被滤波，缩放和调制，并且数据输出被补偿，使得校正输出 获得具有显着降低的量化误差。

公开(公告)号：EP0725446A1

公开(公告)日：1996-08-07

申请号：EP96101258.0

申请日：1996-01-30

申请人： MOTOROLA, INC.

发明人： Mamileti, Lakshmikant

IPC分类号： H01L29/739

CPC分类号： H01L29/7395

摘要： An insulated gate semiconductor device (10) is formed having a buffer layer (13) having a graded dopant profile. The graded dopant profile improves the reverse blocking voltage of the device (10) while maintaining the switching speed.

摘要翻译： 形成具有缓冲层（13）的绝缘栅半导体器件（10），该缓冲层具有渐变的掺杂剂分布。 分级掺杂物分布改善了器件（10）的反向阻断电压，同时保持了开关速度。