公开(公告)号：EP0750399A3

公开(公告)日：1997-06-25

申请号：EP96109959.5

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  King, Barry ,  Page, Andrew ,  Golding, Paul

IPC分类号： H03M13/00 ,  H04L1/00 ,  G06F11/10

CPC分类号： H04L1/0057 ,  G06F11/10 ,  H03M13/09 ,  H03M13/6569

摘要： A cyclic redundancy coder (10) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The cyclic redundancy coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a bit of a cyclic redundancy code word. A tap register (16) stores a tap position indicator indicative of tap positions in the cyclic redundancy code word that are subject to a logical operation. An input (18) provides input data to the cyclic redundancy coder. A logic feedback network (20-28) receives the data from the input and provides the logical operation. The logic feedback network also provides a plurality of data bits generated in response to the input data and each bit contained in each storage element identified by the tap position indicator. The cyclic redundancy code word is produced by applying at least one of the plurality of data bits to one storage element that is adjacent a tap position.

摘要翻译： 循环冗余编码器（10）被布置为将诸如DSP之类的处理器中所需的处理步骤的数量最小化以实现循环冗余编码功能。 循环冗余编码器（10）包括具有多个存储元件的移位寄存器（12），每个存储元件用于存储循环冗余码字的位。 抽头寄存器（16）存储指示经历逻辑操作的循环冗余码字中的抽头位置的抽头位置指示符。 输入（18）向循环冗余编码器提供输入数据。 逻辑反馈网络（20-28）从输入接收数据并提供逻辑操作。 逻辑反馈网络还提供响应于输入数据和包含在由抽头位置指示器识别的每个存储元件中的每个比特产生的多个数据比特。 循环冗余码字通过将多个数据位中的至少一个应用于与抽头位置相邻的一个存储元件来产生。

公开(公告)号：EP0849918A2

公开(公告)日：1998-06-24

申请号：EP97116479.3

申请日：1997-09-22

申请人： MOTOROLA LTD

发明人： Bennett, Irwin Russell ,  Page, Andrew ,  Golding, Paul ,  Benn, Howard Peter

IPC分类号： H04L25/06

CPC分类号： H04L25/067

摘要： The digital radio receiver processes received signals by first determining the values of data bits contained in the received signals. Second, the data bits are assessed a level of confidence to be applied to the data bits. This assessment is done at a group level and applied to each of the data bits contained within that group.

摘要翻译： 数字无线电接收机通过首先确定包含在接收信号中的数据位的值来处理接收信号。 第二，对数据位进行评估以应用于数据位的置信水平。 此评估在组级别完成，并应用于该组中包含的每个数据位。

公开(公告)号：EP0750316A3

公开(公告)日：1998-04-08

申请号：EP96109958.7

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  Page, Andrew ,  King, Barry ,  Golding, Paul

IPC分类号： G11C19/00

CPC分类号： G06F9/30032 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/583 ,  G11C19/00 ,  H04L9/0662 ,  H04L2209/04 ,  H04L2209/12

摘要： A feedback and shift unit is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a particular operating function, such as a linear feedback shift or a stepping function used by encryption algorithms. The feedback and shift unit (50) comprises a linear feedback shift register (52) for storing a value of the feedback and shift unit. A tap register (56) stores a tap position indicator indicative of tap positions for the feedback and shift unit (50). An input provides data to the feedback and shift unit. A feedback matrix, coupled to receive the data from the input, provides data bits, generated in response to the data and the tap position indicator, that are shifted into the linear feedback shift register (52) to form the value stored therein.

公开(公告)号：EP0750316A2

公开(公告)日：1996-12-27

申请号：EP96109958.7

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  Page, Andrew ,  King, Barry ,  Golding, Paul

IPC分类号： G11C19/00

CPC分类号： G06F9/30032 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/583 ,  G11C19/00 ,  H04L9/0662 ,  H04L2209/04 ,  H04L2209/12

摘要： A feedback and shift unit is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a particular operating function, such as a linear feedback shift or a stepping function used by encryption algorithms. The feedback and shift unit (50) comprises a linear feedback shift register (52) for storing a value of the feedback and shift unit. A tap register (56) stores a tap position indicator indicative of tap positions for the feedback and shift unit (50). An input provides data to the feedback and shift unit. A feedback matrix, coupled to receive the data from the input, provides data bits, generated in response to the data and the tap position indicator, that are shifted into the linear feedback shift register (52) to form the value stored therein.

摘要翻译： 布置反馈和移位单元以将处理器（例如DSP）中所需的处理步骤的数量减至最少，以实现特定的操作功能，例如由加密算法使用的线性反馈移位或步进功能。 反馈和移位单元（50）包括用于存储反馈和移位单元的值的线性反馈移位寄存器（52）。 抽头寄存器（56）存储指示反馈和移位单元（50）的抽头位置的抽头位置指示器。 一个输入提供反馈和移位单元的数据。 耦合以从输入接收数据的反馈矩阵提供响应于数据和抽头位置指示符产生的数据位，其被移入线性反馈移位寄存器（52）以形成其中存储的值。

公开(公告)号：EP0849918A3

公开(公告)日：2000-12-27

申请号：EP97116479.3

申请日：1997-09-22

申请人： MOTOROLA LTD

发明人： Bennett, Irwin Russell ,  Page, Andrew ,  Golding, Paul ,  Benn, Howard Peter

IPC分类号： H04L25/06

CPC分类号： H04L25/067

摘要： The digital radio receiver processes received signals by first determining the values of data bits contained in the received signals. Second, the data bits are assessed a level of confidence to be applied to the data bits. This assessment is done at a group level and applied to each of the data bits contained within that group.

公开(公告)号：EP0750401A3

公开(公告)日：1997-06-25

申请号：EP96109957.9

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  Golding, Paul ,  King, Barry ,  Page, Andrew

IPC分类号： H03M13/12 ,  H04L1/00 ,  G06F11/10

CPC分类号： H04L1/0059 ,  G06F11/10 ,  H03M13/23 ,  H03M13/6513 ,  H03M13/6516 ,  H04L1/0043

摘要： A convolutional coder (10) for generating a convolutional code (14) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The convolutional coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a data bit. First (20) and second (22) tap registers each store a tap position indicator indicative of tap positions in the shift register that are subject to a logical operation. an input (17) shifts input data into the convolutional coder (10). A logic network (11), coupled to receive the input data and arranged to provide the logical operation, has first (g0) and second (g1) outputs for providing, respectively, first and second output data bits that form the convolutional code (14); The first output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the first tap position indicator and the second output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the second tap position indicator.

公开(公告)号：EP0750401A2

公开(公告)日：1996-12-27

申请号：EP96109957.9

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  Golding, Paul ,  King, Barry ,  Page, Andrew

IPC分类号： H03M13/12 ,  H04L1/00 ,  G06F11/10

CPC分类号： H04L1/0059 ,  G06F11/10 ,  H03M13/23 ,  H03M13/6513 ,  H03M13/6516 ,  H04L1/0043

摘要： A convolutional coder (10) for generating a convolutional code (14) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The convolutional coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a data bit. First (20) and second (22) tap registers each store a tap position indicator indicative of tap positions in the shift register that are subject to a logical operation. an input (17) shifts input data into the convolutional coder (10). A logic network (11), coupled to receive the input data and arranged to provide the logical operation, has first (g0) and second (g1) outputs for providing, respectively, first and second output data bits that form the convolutional code (14); The first output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the first tap position indicator and the second output data bit is generated in response to the input data and the logical combination of each data bit stored in each storage element identified by the second tap position indicator.

摘要翻译： 用于产生卷积码（14）的卷积编码器（10）被布置成将处理器（例如DSP）中所需的处理步骤的数量减至最小以实现循环冗余编码功能。 卷积编码器（10）包括具有多个存储元件的移位寄存器（12），每个存储元件用于存储数据位。 第一（20）和第二（22）抽头寄存器每个存储指示在移位寄存器中进行逻辑运算的抽头位置的抽头位置指示器。 输入（17）将输入数据移入卷积编码器（10）。 耦合以接收输入数据并被布置成提供逻辑操作的逻辑网络（11）具有第一（g0）和第二（g1）输出，用于分别提供形成卷积码的第一和第二输出数据比特（14） ）; 响应于输入数据生成第一输出数据位，并且响应于输入数据和逻辑值产生存储在由第一抽头位置指示符标识的每个存储元件中的每个数据位的逻辑组合，并且第二输出数据位被生成 由存储在由第二抽头位置指示符标识的每个存储元件中的每个数据位的组合。

公开(公告)号：EP0750399A2

公开(公告)日：1996-12-27

申请号：EP96109959.5

申请日：1996-06-20

申请人： MOTOROLA LTD

发明人： Bennett, Irwin ,  King, Barry ,  Page, Andrew ,  Golding, Paul

IPC分类号： H03M13/00 ,  H04L1/00 ,  G06F11/10

CPC分类号： H04L1/0057 ,  G06F11/10 ,  H03M13/09 ,  H03M13/6569

摘要： A cyclic redundancy coder (10) is arranged to reduce to a minimum the number of processing steps required in a processor, such as a DSP, to achieve a cyclic redundancy coding function. The cyclic redundancy coder (10) comprises a shift register (12) having a plurality of storage elements each for storing a bit of a cyclic redundancy code word. A tap register (16) stores a tap position indicator indicative of tap positions in the cyclic redundancy code word that are subject to a logical operation. An input (18) provides input data to the cyclic redundancy coder. A logic feedback network (20-28) receives the data from the input and provides the logical operation. The logic feedback network also provides a plurality of data bits generated in response to the input data and each bit contained in each storage element identified by the tap position indicator. The cyclic redundancy code word is produced by applying at least one of the plurality of data bits to one storage element that is adjacent a tap position.