公开(公告)号：EP0087266A2

公开(公告)日：1983-08-31

申请号：EP83300778.4

申请日：1983-02-16

申请人： Honeywell Bull Inc.

发明人： Brown, Richard P. ,  Lemay, Richard A. ,  Steiner, Lewis G. ,  Woods, William E.

IPC分类号： G06F13/00

CPC分类号： G06F13/18

摘要： A priority resolution circuit has four flip-flops CPF, SIF, CIF, and FIF for the four possible requesting units. Setting a low priority flip-flop, e.g. CPF, prevents later setting of a higher priority one by gates 33 to 35, but a high priority one can be set substantially simultaneously with a low priority one. Output gates CPG, SIG, CIG, select the highest priority flip-flop which is set. The setting of any flip-flop fires a timing circuit by pulse TCF, and this enables the gates CPG, SIG, CIG by pulse CLR after all possible transients have decayed. The timing circuit may have its timing controlled by the selected unit (CPU, SIP, CIP, or MBA) via a selector controlled by the flip-flops CPF, SIF, CIF, and FIF.

摘要翻译： 优先级分辨率电路具有四个触发器CPF，SIF，CIF和FIF，用于四个可能的请求单元。 设置低优先级触发器，例如 CPF防止稍后通过门33至35设置较高优先级，但是可以与低优先级基本上同时设置高优先权。 输出门CPG，SIG，CIG，选择设置的最高优先级触发器。 任何触发器的设置通过脉冲TCF触发定时电路，并且这在所有可能的瞬变衰减之后通过脉冲CLR使门CPG，SIG，CIG成为可能。 定时电路可以通过由触发器CPF，SIF，CIF和FIF控制的选择器由所选择的单元（CPU，SIP，CIP或MBA）控制其定时。

公开(公告)号：EP0072179A2

公开(公告)日：1983-02-16

申请号：EP82304086.0

申请日：1982-08-03

申请人： Honeywell Bull Inc.

发明人： Webster, Marvin K. ,  Flynn, Richard T. ,  Porter, Marion G. ,  Seminsky, George M.

IPC分类号： G06F12/08

CPC分类号： G06F12/0808

摘要： A cache memory comprises a directory 202 and a data store 201. The n-bit portion of a desired address from an associated CPU selects a location in directory 202, and the m-bit address portions in the 4 levels I to IV of that location are compared at 203 with the m-bit portion of the desired address. On a match, the corresponding level of the corresponding location of the data store 201 is accessed to access the desired word.
The cache words should mirror the contents of the main memory, but the latter may be changed by e.g. another CPU or an IOC, and the resulting invalid addresses must be cleared from the cache memory. This is done by searching the directory 202 for an invalid address during the second half of a cache cycle, after the directory has been searched to determine whether the desired word is in the cache and while that desired word is being accessed in the cache store 201. If an invalid address is found, the second half of the next cache cycle is used to clear it from the cache, by resetting the full/empty indicator in the directory control portion C for that level and that location.

摘要翻译： 高速缓冲存储器包括目录202和数据存储201.来自相关CPU的期望地址的n位部分选择目录202中的位置，并且该位置的4级I至IV中的m位地址部分 在203与所需地址的m位部分进行比较。 在匹配时，访问数据存储201的对应位置的相应级别以访问所需的字。 ... 缓存字应该镜像主存储器的内容，但后者可以通过例如 另一个CPU或IOC，并且所得到的无效地址必须从缓存中清除。 这是通过在高速缓存周期的后半部分中搜索目录202的无效地址之后，在目录被搜索以确定期望的字是否在高速缓存中并且在该高速缓存存储器201中正在访问该期望的字的情况下 如果发现无效地址，则通过重置目录控制部分C中该级别和该位置的完整/空指示符，将下一个高速缓存周期的后半部分从高速缓存中清除。

公开(公告)号：EP0032136A2

公开(公告)日：1981-07-15

申请号：EP81300076.7

申请日：1981-01-08

申请人： Honeywell Bull Inc.

发明人： Johnson, Robert B. ,  Nibby, Chester M. Jr. ,  Moore, Dana W.

IPC分类号： G06F13/00

CPC分类号： G06F12/04 ,  G06F12/0607

摘要： A memory system comprises a plurality of rows (RASO-RAS7) of memory chips, 22 chips per row (for 22-bit words). Each chip contains 64K bits, giving 64K words per row. The least significant bits (bits 21 and 22) of the word address select the row of chips, so that successive word addresses are in successive rows cyclically (in the lower half of memory). These 2 bits are decoded to select the row containing the desired word and the next row (in cycle sequence), and the RAM chip address is passed to both selected rows. Thus the word in the next address up from the selected one is selected in addition to the selected word. An increment-by-1 circuit is provided to increment the address to the "next" row when the last row is selected, so that if word 3 is selected, word 4 and not word 0 will also be selected. The size of the increment-by-1 circuit is limited, and a boundary condition detection circuit is provided to detect when an overflow occurs and inhibit the sleection of the second selected word, which is in this instance not the next word up.

摘要翻译： 存储器系统包括存储器芯片的多行（RASO-RAS7），每行22个码片（用于22位字）。 每个芯片包含64K位，每行64K字。 字地址的最低有效位（位21和22）选择芯片行，使得连续字地址在循环（在存储器的下半部分）中是连续的字地址。 这两个位被解码以选择包含所需字和下一行的行（以周期顺序，并且RAM芯片地址被传递到两个选定的行，因此，从所选择的一个中增加下一个地址中的字除外） 当选择最后一行时，提供一个递增1电路以将地址递增到“下一个”行，以便如果选择了第3个字，则也将选择字4而不是字0。 提供用于检测何时发生溢出并且禁止电路的递增1的大小被限制，并且边界条件检测电路是第二个选择的单词，这在这种情况下不是下一个单词向上。

公开(公告)号：EP0264077A3

公开(公告)日：1991-01-30

申请号：EP87114769.0

申请日：1987-10-09

申请人： Honeywell Bull Inc.

发明人： Lemay, Richard A. ,  Tague, Steven A. ,  Izbicki, Kenneth J. ,  Woods, William E.

IPC分类号： G06F7/00

CPC分类号： G06F7/78

摘要： A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the address already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be transferred to the buffer address register for read out.

公开(公告)号：EP0299514A3

公开(公告)日：1990-02-28

申请号：EP88111410.2

申请日：1988-07-15

申请人： Honeywell Bull Inc.

发明人： Morris, Scott S. ,  Daniels, George R.

IPC分类号： B41J3/58 ,  B41F5/06

CPC分类号： B41J3/60 ,  G03G15/238 ,  G03G2215/00455 ,  G03G2215/00814 ,  G03G2215/00818

摘要： A printer apparatus having two-sided printing capability is taught. Two printing mechanisms (14, 15) are provided that can simultaneously print both sides of roll paper (13). The printing mechanisms are physically oriented with respect to each other and to a simple paper handling/routing mechanism comprised of rollers so that when only one printing mechanism (14) is installed to provide only one-side printing, the paper handling mechanism need not be modified but the roll paper (13) is merely routed differently around the rollers. Retroactively, a second printing mechanism (15) may simply be installed in the printer for two-sided printing and the roll paper is routed around the rollers differently to route the roll paper to and from the second printing mechanism.

公开(公告)号：EP0321776A2

公开(公告)日：1989-06-28

申请号：EP88120341.8

申请日：1988-12-06

申请人： Honeywell Bull Inc.

发明人： McNally, Lance ,  Booth, Anthony J. ,  Morely, Peter

IPC分类号： G06F11/20 ,  H04L1/22

CPC分类号： G06F11/2005 ,  G06F11/2035

摘要： A communication data system is designed for resiliency by automatically replacing or bypassing defective units. The system includes a number of input/output terminals which are connected to MODEMs through a relay bank. The MODEMs send serial data to a serial I/O module which converts the serial data to bytes which it places on a VMEbus. A network processor sends the data from the VMEbus to a general purpose computer which places the data into the communications network. A general purpose computer or a back-up general purpose computer may detect a defective communication link and automatically switch to a back-up network computer, or cause a control module to switch the relay module to a spare MODEM and spare SIO. The control module may also generate a remote line test to the link between the MODEM and the terminal to determine if that link is defective.

摘要翻译： 通信数据系统通过自动更换或绕过有缺陷的单元而设计用于弹性。 该系统包括通过继电器组连接到MODEM的多个输入/输出端子。 MODEM将串行数据发送到串行I / O模块，将串行数据转换为位于VMEbus上的字节。 网络处理器将数据从VMEbus发送到将数据放入通信网络的通用计算机。 通用计算机或备用通用计算机可以检测有缺陷的通信链路，并自动切换到备用网络计算机，或使控制模块将继电器模块切换到备用MODEM和备用SIO。 控制模块还可以对MODEM和终端之间的链路生成远程线路测试，以确定该链路是否有故障。

公开(公告)号：EP0131277B1

公开(公告)日：1989-05-31

申请号：EP84107914.8

申请日：1984-07-06

申请人： Honeywell Bull Inc.

发明人： Hooker, Lane K. ,  Howell, Thomas H. ,  Ferrell, Charles W.

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/084

公开(公告)号：EP0114523B1

公开(公告)日：1989-01-04

申请号：EP83307916.3

申请日：1983-12-22

申请人： Honeywell Bull Inc.

发明人： Boudreau, Daniel A. ,  Salas, Edward R. ,  Sandini, James M.

IPC分类号： G06F13/36

CPC分类号： G06F13/37 ,  G06F13/378

公开(公告)号：EP0088838B1

公开(公告)日：1988-12-28

申请号：EP82301275.2

申请日：1982-03-12

申请人： Honeywell Bull Inc.

发明人： Crawford, Knute S.

IPC分类号： G06F13/00

CPC分类号： G06F13/122

公开(公告)号：EP0247522A3

公开(公告)日：1988-10-19

申请号：EP87107406

申请日：1987-05-21

申请人： Honeywell Bull Inc.

发明人： Dillon, Richard R. ,  Henneberg, Helmut H. ,  Soares, Antonio P. S. ,  Yoshida, Paul S.

IPC分类号： H05K05/00 ,  H05K07/20 ,  H05K09/00

CPC分类号： H05K7/20554

摘要： What is disclosed is an electronic equipment housing (10,11) that provides easy access to electronic equipment inside via a hinged top panel (19) and a clear plastic safety panel (46) below it. Inside the housing are cable raceways (17,18) at the top front and top rear that are in line with raceways in adjacent housings to permit many cables to be contained inside the housings. The raceways and cables therein do not interfere with convection cooling inside the housings and do not interfere with top access to the equipment. Relatively high heat generating equipment such as power supplies (38) are mounted to one side of the interior of a housing and separate fans (39,40) cool the power supplies with one flow of air, and other equipment in the housing is cooled by a separate flow of air drawn by other fans. One housing (10) is used to house common system equipment and is always located at one end of a line of housings. The common housing (10) has a side mounted connector arrangement, with the connectors being mounted on swing out doors (28,29) to provide access to change the connectors or wiring thereto. The connectors are organized that cables coming from other adjacent housings to the connectors may all be the same length. The front and rear panels (14,54) on all housings have slots (16) that permit cooling air flow, and conductive screening behind the slots (16) minimizes radio frequency interference (RFI). In addition, the top, front and side removable panels have gaskets (15) to suppress RFI.