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    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    1.
    发明授权
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输

    公开(公告)号：EP0667014B1

    公开(公告)日：1998-01-07

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/378

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM
    2.
    发明公开
    ANORDNUNG ZUR DATENÜBERTRAGUNG MIT EINEM PARALLELEN BUSSYSTEM 失效
    安排了并行总线系统中数据传输。

    公开(公告)号：EP0667014A1

    公开(公告)日：1995-08-16

    申请号：EP93923453.0

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13

    CPC分类号： G06F13/368 ,  G06F13/378

    摘要： The invention pertains to a configuration for data transfer with a parallel bus system, consisting of address, data and control buses, and with several units (3, 4, 5, 6) interfacing with them. A first control line (1) is used to send an acknowledge signal (Ready), with which one or more units addressed by a first unit acknowledge accesses in access cycles. A second control line (2) is used to detect addressing errors and accesses to non-existant units and to carry to the first unit an answering signal (SR) from the others indicating whether one of the interfaced units was addressed. To do so the answering signal (SR) has dominant and recessive statuses. During an access cycle only addressed units generate a dominant status. The answering signal (SR) is also used for synchronous multipoint access. The invention is used in bus systems.

    Quasi-fair arbitration scheme with default owner speedup
    3.
    发明公开
    Quasi-fair arbitration scheme with default owner speedup 失效
    具有默认所有权的QUASI-FAIR仲裁方案

    公开(公告)号：EP0366434A3

    公开(公告)日：1991-08-14

    申请号：EP89310982.7

    申请日：1989-10-25

    申请人： Hewlett-Packard Company

    发明人： Milia, Andrew ,  Bahr, Richard G.

    IPC分类号： G06F13/36

    CPC分类号： G06F13/378

    摘要： A decentralized, pipelined, synchronous bus arbitration scheme which allows almost completely fair arbitration between multiple devices competing for the use of a communication bus while allowing the device that last used the bus faster access to the bus if no other device is competing for its use. The arbitration method and apparatus according to the present invention allows all devices that participate in arbitration equal access to the bus with the exception that when bus requests are posted simultaneously the device with the higher priority will always be granted use of the bus first.

    High-speed link for connecting peer systems
    4.
    发明公开
    High-speed link for connecting peer systems 失效
    用于连接对等体系的高速链接

    公开(公告)号：EP0239952A3

    公开(公告)日：1989-11-29

    申请号：EP87104596.9

    申请日：1987-03-27

    申请人： WANG LABORATORIES INC.

    发明人： Trottier, Robert R. ,  Reeder, David A.

    IPC分类号： G06F13/42 ,  G06F13/36 ,  G06F15/16

    CPC分类号： G06F13/378 ,  G06F13/4213

    摘要： A high speed link used to connect peer computer systems (103). The link includes data lines (219) and control lines (221) connected to a device adapter (321) in the I/O system of each of the peer computer systems and logic in each device adapter. The data lines carry data words in parallel; the con- trollines include status lines (203) indicating status of each of the peer systems, arbitration lines (205) for indicating which of the peer systems currently desires to transmit data across the link and whether the link is available, and receiver acquisition lines (207) for specifying which of the peer systems is to receive a transmission and whether the specified system is able to receive the transmission. The logic in the device adapter includes status logic (601, 617) responsive to the status lines for inhibiting a transmission when the receiving peer system is not ready, arbitration logic (801) responsive to the arbitration lines for deciding which peer system may have access to the link at any given time, and receiver acquisition logic (1001) permitting the transmitting device adapter to specify the receiving system, permitting the receiving device adapter to return its address and acknowledge its selection, and permitting the transmitting device adapter to verify the selection and determine whether the receiving system is able to receive data.

    Dispositif pour décentraliser la gestion du bus de transfert de données commun à plusieurs unités d'un système de traitement de l'information
    7.
    发明公开
    Dispositif pour décentraliser la gestion du bus de transfert de données commun à plusieurs unités d'un système de traitement de l'information 失效
    装置共用的数据处理系统的各种单元的传输总线的管理的分散化。

    公开(公告)号：EP0032864A1

    公开(公告)日：1981-07-29

    申请号：EP81400063.4

    申请日：1981-01-19

    申请人： COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB)

    发明人： Vinot, Daniel René

    IPC分类号： G06F3/04

    CPC分类号： G06F13/378

    摘要： Le dispositif est constitué par un ensemble de logiques de commande 12bis distribuées à raison d'une par unité comprenant chacune un circuit de priorité P12 recevant sur une entrée la demande locale RQ;L pour prendre de la maîtrise du bus, l'unité dans laquelle il se trouve et sur les autres entrées l'ensemble des autres demandes externes RQ k émises par les autres unités, la maîtrise du bus étant accordée à l'unité demanderesse dont le circuit de priorité la reconnaît comme étant la plus prioritaire.

    摘要翻译： 1.设备所共有的一个数据处理系统的若干单元中的数据传输总线的管理的下放，单元能够由各个处理器以及存储器的每个处理器可以连接其中，具有控制每个单元 逻辑（12B）的装置以及用于初始化用于服务到其他单元或响应（RESPONSE）到由其它单元请求服务的呼叫的呼叫（START）的阶段，每个控制逻辑（12b）中设置有一个和相同的优先级 电路（12），在一个输入端接收所述本地呼叫（RQiL）从单元本身，每个控制逻辑被用于递送由资格电路的转换产生一个合格的呼叫信号（RQiE）的设置有资格的电路（13） （13）的本地呼叫（RQiL）作为单元的至极专业化的函数发现和的所述数据传送总线的可用性状态，DASS优先电路（12）的另外的多个接收 s的其它输入 - 以及资格输出 - 整个外部呼叫（RQk）反式通过其它单元mitted的，总线的控制被调用时单元其优先级电路识别相同为具有最高优先级赋予 供应符合条件的呼叫信号（RQiE）。

    ANORDNUNG MIT MEHREREN AKTIVEN UND PASSIVEN BUSTEILNEHMERN
    8.
    发明授权
    ANORDNUNG MIT MEHREREN AKTIVEN UND PASSIVEN BUSTEILNEHMERN 失效
    具有多个活动和被动站安排

    公开(公告)号：EP0667015B1

    公开(公告)日：1997-03-05

    申请号：EP93924011.5

    申请日：1993-10-29

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： ABERT, Michael ,  BLOCK, Siegfried ,  BOZENHARDT, Johannes ,  LEIGSNERING, Franz ,  PFATTEICHER, Werner ,  SCHEWE, Franz-Clemens

    IPC分类号： G06F13/378 ,  G06F13/368

    CPC分类号： G06F13/378 ,  G06F13/1652 ,  G06F13/368

    摘要： The invention pertains to a configuration with several active and passive bus users (MP1, MP2, SP1, SP2), each of which is allocated a memory (S1, S2, SS1, SS2), with its own memory area (SB1, SB2, SB3, SB4), where each bus user (MP1, MP2, SP1, SP2) has read access to its own memory area (SB1, SB2, SB3, SB4) and each active bus user (MP1, MP2) has write access to every memory area (SB1, SB2, SB3, SB4). A control line (ML) is provided for sending an indicative signal (SR) which indicates to the active bus users (MP1, MP2) accessing the memory areas (SB1, SB2, SB3, SB4) whether data in the memory areas (SB1, SB2, SB3, SB4) have already been written in, as the answering signal (SR) has dominant and recessive statuses and outside of access cycles all bus users produce a dominant status, during a cycle of access to the memory areas (SB1, SB2, SB3, SB4) only the bus users (MP1, MP2, SP1, SP2) in whose memory areas (SB1, SB2, SB3, SB4) the data have not yet been written in produce such a signal. The invention is used in automation systems.