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公开(公告)号：EP0231526A2
公开(公告)日：1987-08-12
申请号：EP86118136.0
申请日：1986-12-30
申请人： HITACHI, LTD.
CPC分类号： G06F15/8076 , G06F9/30036 , G06F9/3877
摘要： A multi-processor system including a main storage (1) for storing instructions and data, a master processor (3) for supplying to a slave processor (4) data required for the processing to be executed by the slave processor and commanding initiation of the processing, the master processor further having a function to test the operation state of the slave processor and perform processing by utilizing the result of th processing executed by the slave processor. The slave processor (4) initiates the processing under the command of the master processor and has a function to inform of the master processor of completion of the processing. The slave processor has a function to execute a pause instruction for suspending temporarily activation of processing for a succeeding instruction and setting a pause indication at an indicator (453,454,455) of the slave processor. When the pause indication is set in the slave processor, the master processor has a function to reset this indication to release the slave processor from the pause state. When the pause state indication is not set, the master processor executes a clearing instruction supplied from the main storage for suspending the function to activate the succeeding instruction. The processor is further imparted with a function for setting at the indicator an indication instruction indicating completion of execution of the succeeding instruction. The master processor is imparted with a function to reset the indication of completed execution of instruction set at the slave processor and otherwise execute an indication resetting instruction for suspending activation of a succeeding instruction.
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公开(公告)号：EP0208870A1
公开(公告)日：1987-01-21
申请号：EP86106710.6
申请日：1981-07-21
申请人： HITACHI, LTD.
IPC分类号： G06F15/347 , G06F9/38
CPC分类号： G06F15/8084 , G06F9/3867
摘要： The vector processor according to the present invention includes a read address counter and a write address counter in an address circuit for each vector register, so that a read operation and a write operation are performed in parallel to the same vector register by these adress counters.
摘要翻译： 根据本发明的矢量处理器在每个向量寄存器的地址电路中包括读地址计数器和写地址计数器，从而通过这些地址计数器并行地执行读操作和写操作。
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公开(公告)号：EP0141908A2
公开(公告)日：1985-05-22
申请号：EP84108740.6
申请日：1984-07-24
申请人： HITACHI, LTD.
IPC分类号： G06F15/347 , G06F15/06 , G06F9/38
CPC分类号： G06F15/8076 , G06F9/3885
摘要： @ A data processing apparatus comprises a plurality of sub-systems (30a-30d) each including at least one arithmetic unit (38a-38d), a plurality of registers (35a-35d), a first selector (33a-33d) for receiving vector data and selectively outputting the input data to the registers, and a second selector (34a-34d) for receiving the vector data from the registers and selectively outputting the input data to a plurality of output lines. The data output of the arithmetic unit in each sub-system is supplied to the first selector in the same sub-system and the first selector in other sub-system, and the arithmetic unit in each sub-system receives the output data from the second selector in the same sub-system. The data output from the second selector in at least one sub-system is supplied to a main storage unit (10), and the data output from the main storage unit is supplied to the first selector in at least one sub-system.
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公开(公告)号：EP0255857B1
公开(公告)日：1994-09-14
申请号：EP87107576.8
申请日：1987-05-22
申请人： HITACHI, LTD.
CPC分类号： G06F9/54 , G06F15/161
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公开(公告)号：EP0255857A3
公开(公告)日：1990-10-31
申请号：EP87107576.8
申请日：1987-05-22
申请人： HITACHI, LTD.
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system is disclosed which comprises a plurality of processors (1) each for executing at least one of a plurality of mutually associated programs and a transfer circuit (3) connected to the processors, for transferring the data outputted from any one of the programs during execution of one program by any one of the processors (1) to other processors (1) to which a receiving program is allotted, in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.
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26.发明公开Parallel computer system capable of asynchronous data transmission 失效Parallelrechnersystem，geeignetfürasynchroneDatenübertragung。
公开(公告)号：EP0258650A2
公开(公告)日：1988-03-09
申请号：EP87111124.1
申请日：1987-07-31
申请人： HITACHI, LTD.
发明人： Tanaka, Teruo , Hamanaka, Naoki , Omoda, Koichiro , Nagashima, Shigeo , Muramatsu, Akira , Yoshihara, Ikuo , Nakao, Kazuo , Nakagoshi, Junji , Ojima, Kazuo
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： Herein disclosed is a parallel computer system having a plurality of processors (2), each of which is equipped with means (5) receiving from an interconnecting network and for storing pairs of a data signal and a data identification code predetermined for the data signal and for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译： 这里公开的是具有多个处理器（2）的并行计算机系统，每个处理器（2）配备有从互连网络接收并用于存储数据信号对和数据信号预定的数据识别码的装置（5） 用于读取属于具有由数据读出指令指定的数据识别码的一对中的一个的数据信号。
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公开(公告)号：EP0131284A3
公开(公告)日：1988-01-07
申请号：EP84107937
申请日：1984-07-06
申请人： HITACHI, LTD.
发明人： Omoda, Koichiro , Nagashima, Shigeo
IPC分类号： G06F15/347
CPC分类号： G06F15/8084
摘要： A storage control apparatus for sequentially reading out each data element of vector data stored in a main storage unit (1-1-1) and for writing the readout data elements sequentially in the corresponding register elements of the vector register (VR1) disposed in a vector processor is disclosed. In the apparatus only the data element indicated as the write data by the mask information among the readout data elements are stored from the main storage unit (1-1-1) to the pertinent register elements of the vector register (VR1) in the vector processor based on the mask information which indicates whether or not the write operation is required (for example, "1" indicates that the write operation is necessary and "0" indicates that the write operation is unnecessary). When the mask information indicates that the write operation is not required, the storage control apparatus controls operationsto prevent the memory bank of the main storage from being set to the busy state, thereby eliminating the memory bank conflict which should not take place in accordance with the intrinsic system characteristics.
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公开(公告)号：EP0131284A2
公开(公告)日：1985-01-16
申请号：EP84107937.9
申请日：1984-07-06
申请人： HITACHI, LTD.
发明人： Omoda, Koichiro , Nagashima, Shigeo
IPC分类号： G06F15/347
CPC分类号： G06F15/8084
摘要： A storage control apparatus for sequentially reading out each data element of vector data stored in a main storage unit (1-1-1) and for writing the readout data elements sequentially in the corresponding register elements of the vector register (VR1) disposed in a vector processor is disclosed. In the apparatus only the data element indicated as the write data by the mask information among the readout data elements are stored from the main storage unit (1-1-1) to the pertinent register elements of the vector register (VR1) in the vector processor based on the mask information which indicates whether or not the write operation is required (for example, "1" indicates that the write operation is necessary and "0" indicates that the write operation is unnecessary). When the mask information indicates that the write operation is not required, the storage control apparatus controls operationsto prevent the memory bank of the main storage from being set to the busy state, thereby eliminating the memory bank conflict which should not take place in accordance with the intrinsic system characteristics.
摘要翻译： 一种存储控制装置，用于顺序地读出存储在主存储单元（1-1-1）中的矢量数据的每个数据元素，并将读出的数据元素顺序地写入到设置在主存储单元（1-1-1）中的向量寄存器（VR1）的相应寄存器元素中 向量处理器被公开。 在该装置中，只有通过读出数据元素中的掩模信息指示为写入数据的数据元素从主存储单元（1-1-1）存储到向量中的向量寄存器（VR1）的相关寄存器元素 处理器基于指示是否需要写入操作的掩码信息（例如，“1”表示写入操作是必需的，“0”表示不需要写入操作）。 当掩模信息指示不需要写入操作时，存储控制装置控制操作以防止主存储器的存储体被设置为忙状态，从而消除了不应该根据 内在系统特征。
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公开(公告)号：EP0063361A2
公开(公告)日：1982-10-27
申请号：EP82103151.5
申请日：1982-04-14
申请人： Hitachi, Ltd.
IPC分类号： G06F7/52
CPC分类号： G06F7/535 , G06F7/49942 , G06F2207/3884 , G06F2207/5355
摘要： An approximate quotient-correcting circuit wherein ah approximate quotient Q H , a divisor D, and the least significant bit of the fraction part of a dividend N are read out; the approximate quotient Q H and the divisor D are multiplied; it is decided that the lower m digits of Q H x D are not all 'O' and that the m-th significant bit of Q H x D is coincident with the m-th significant bit of N; and when the result of the decision is positive, Q H - 2 -m is provided as a quotient.
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