公开(公告)号：EP0834115A1

公开(公告)日：1998-04-08

申请号：EP96915967.0

申请日：1996-06-04

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： PRANGE, Stefan ,  THEWES, Roland ,  WOHLRAB, Erdmute ,  WEBER, Werner

IPC分类号： G06F7 ,  H03K19

CPC分类号： G06F7/5013 ,  G06F7/523 ,  G06F2207/4818 ,  H03K19/0813

摘要： The invention relates to a circuit by means of which all logic elements which can be represented in the form of a threshold equation can be produced. To this end, parallel transistors (T1, T2, T3, ..., Tn) of a transistor unit are dimensioned so that the transverse currents (It1, It2, It3, ..., Itn) flowing through the transistors (T1, T2, T3, ..., Tn) represents a weighted summand of a first term of the threshold equation. A second term in the threshold equation is formed by a reference current IR representing the value of the second term. An evaluation unit (BE) compares a total current found from the sum of the transverse currents (It1, It2, It3, ..., Itn with the reference current IR. The result of evaluation is provided in the form of a stable output signal at an output of the evaluation unit (BE).