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    Multiple-input binary adder
    1.
    发明公开
    Multiple-input binary adder 失效
    Bin n。。。。。。。。。。。。

    公开(公告)号：EP0721159A1

    公开(公告)日：1996-07-10

    申请号：EP95120657.2

    申请日：1995-12-28

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Mahant-Shetti, Shivaling S. ,  Lemonds, Carl E., Jr.

    IPC分类号： G06F7/60 ,  G06F7/50 ,  G06F7/52

    CPC分类号： G06F7/5013 ,  G06F7/607 ,  G06F2207/4818

    摘要： A current mode circuit for the collumn-wise addition of partial product bits in a multiplier. The circuit includes a plurality of digital input terminals PP1-PP15 for receiving a binary input signal. A plurality of transistors 20 are each coupled to an input terminal and produce a current of i0 into a summing node 24 when the input terminal coupled thereto has a binary one signal thereon and no current when the input signal is a binary zero. The current in the summing node 24 is shunted to ground by a diode 30. A high order sum bit C3OUT is produced by a current sensing circuit including transistors 32 and 34 when the current into the summing node is equal or greater than 8i0. A second order sum bit C2OUT is produced by a current sensing circuit including transistors 42, 52 and 54 when the current in the summing node is greater than or equal to 12i0 or greater than or equal to 4i0 but less than 8i0. A third order sum bit C1OUT is produced by a current sensing circuit including transistors 44, 66, 60 and 68 when the current into the summing node is equal to 2i0, 3i0, 6i0, 7i0, 10i0, 11i0, 14i0, or 15i0. A fourth order sum bit SUM is produced by a current sensing circuit including transistors 46, 62, 74, 78, and 80 when the current into the summing node is equal to i0, 3i0, 5i0, 7i0, 9i0, 11i0, 13i0, or 15I0.

    摘要翻译： 用于在乘法器中逐行添加部分积位的电流模式电路。 该电路包括用于接收二进制输入信号的多个数字输入端子PP1-PP15。 多个晶体管20各自耦合到输入端，并且当耦合到其上的输入端具有二进制一个信号并且当输入信号是二进制零时没有电流，将i0的电流产生到求和节点24中。 求和节点24中的电流由二极管30分流到地。当进入求和节点的电流等于或大于8i0时，由包括晶体管32和34的电流检测电路产生高阶和位C3OUT。 当求和节点中的电流大于或等于12i0或大于或等于4i0但小于8i0时，由包括晶体管42,42和54的电流感测电路产生第二级和位C2OUT。 当进入求和节点的电流等于2i0,3i0,6i0,7i0,10i0,11i0,14i0或15i0时，由包括晶体管44,46,60和68的电流检测电路产生第三级和位C1OUT。 当进入求和节点的电流等于i0,3i0,5i0,7i0,9i0,111i0，13i0或...时，包括晶体管46,62,74,78和80的电流检测电路产生第四级和位SUM 15I0。

    SCHALTUNGSANORDNUNG ZUR REALISIERUNG VON DURCH SCHWELLENWERTGLEICHUNGEN DARSTELLBAREN LOGIKELEMENTEN
    3.
    发明公开
    SCHALTUNGSANORDNUNG ZUR REALISIERUNG VON DURCH SCHWELLENWERTGLEICHUNGEN DARSTELLBAREN LOGIKELEMENTEN 失效
    电路用于实现阈值方程的显示逻辑单元

    公开(公告)号：EP0834115A1

    公开(公告)日：1998-04-08

    申请号：EP96915967.0

    申请日：1996-06-04

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： PRANGE, Stefan ,  THEWES, Roland ,  WOHLRAB, Erdmute ,  WEBER, Werner

    IPC分类号： G06F7 ,  H03K19

    CPC分类号： G06F7/5013 ,  G06F7/523 ,  G06F2207/4818 ,  H03K19/0813

    摘要： The invention relates to a circuit by means of which all logic elements which can be represented in the form of a threshold equation can be produced. To this end, parallel transistors (T1, T2, T3, ..., Tn) of a transistor unit are dimensioned so that the transverse currents (It1, It2, It3, ..., Itn) flowing through the transistors (T1, T2, T3, ..., Tn) represents a weighted summand of a first term of the threshold equation. A second term in the threshold equation is formed by a reference current IR representing the value of the second term. An evaluation unit (BE) compares a total current found from the sum of the transverse currents (It1, It2, It3, ..., Itn with the reference current IR. The result of evaluation is provided in the form of a stable output signal at an output of the evaluation unit (BE).