Abstract:
The invention relates to a biosensor for detecting nucleic acids, comprising at least two units for immobilizing nucleic acids and one electrical detection circuit. Said units are electroconductive and electrically insulated from one another. The units are provided with first nucleic acid molecules that are present as single-stranded molecules and that are capable of binding second nucleic acids to be detected. These scavenger molecules are provided with a redox-active marker that is capable of producing a detectable signal. The electrical detection circuit is adapted to detect by means of the marker any nucleic acid molecules bound to the scavenger molecules.
Abstract:
The invention relates to a circuit which compares a quantity supplied by a first neuron MOS field effect transistor (M1) with a reference value provided by a reference source (R). To this end there is a current mirror (SP) facilitating a comparison between a second current (I2) supplied by a reference transistor (R) and a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The assessment circuit is activated or decoupled by a first switch unit (S1) and a second switch unit (S2). This ensures that no current flows in the evaluation circuit in the inoperative position. The result of comparison is applied to an inverter stage (IS). As the inverter stage (IS) is decoupled from the evaluation circuit by the first switch unit (S1), there is never an undefined level at the inverter stage (IS). Advantage can be taken of this during data processing in subsequent stages.
Abstract:
The invention concerns a semiconductor neuron in which input electrodes are coupled capacitively to a floating gate (FG) of which the potential controls the current of a MOSFET (NT), and in which a respective neuron input (E1 ... E4) can be connected to partial electrodes (1 ... 7) of a respective input electrode such that the entire surface of the partial electrodes connected to the respective neuron input corresponds to a respective weight of the neuron input. The invention combines the high processing speed of a hardware neuron with the flexibility of a software neuron.
Abstract:
The invention relates to a circuit by means of which two electrical quantities in the form of a first transverse current (I1) and a second transverse current (I2) can be mutually compared. The circuit has a first inverter stage (n1, p1). An output (50, 51) of the two inverter stages (n1, p1, n2, p2) are coupled to an input of the other inverter stage (52, 53). Between the two outputs of the two inverter stages (n1, p2) there is a reset unit (5) which, on being activated, starts the current comparison. If the reset unit (5) is deactivated, the output datum obtained during the evaluation remains stable.
Abstract:
The invention relates to a sensor arrangement comprising a control circuit, embodied such that at least one sensor electrode can be charged and/or discharged therewith and a comparator unit for the comparison of a provided voltage for the at least one electrode with a reference voltage. A duration necessary for the charging/discharging of the at least one sensor electrode is determined, whereby, from the determined duration, it is determined whether a sensor event, in the form of a hybridisation between trap molecules and the particles for recording, has occurred.
Abstract:
The invention relates to a biosensor array (600, 700, 1000, 1100, 1200, 2200, 2400, 2500, 2600, 2700, 2800, 2900, 3000) and a method for operating a biosensor array. The biosensor array comprises a substrate (601) and a plurality of biosensor fields (602) that are arranged on said substrate, each of said fields having a first connection (603) and a second connection (604). At least one of at least one first conductor (605) and at least one of at least one second conductor (606) is coupled to at least two of the biosensor fields.
Abstract:
The invention relates to a magnetoresistive memory having improved interference immunity while keeping the chip surface small. Interference immunity is improved by arranging word lines vertically between two complementary bit lines. Also, a magnetoresistive memory system of a regular cell is provided between a bit line and a word line, and a pertaining magnetoresistive layer system of a complementary memory cell is provided between the complementary bit line and the word line.
Abstract:
To skip any distances, a device for skip addressing bit or word lines (11 to 1N) of a serially operating store has two open control loops (2, 3) allocated to the lines together and one linkage component (41 to 4N) per line, where each linkage component is connected precisely to one pair of outputs of the two open control loops and one line is precisely addressed when the bit "1" is applied to said pair of outputs.
Abstract:
The object of the application is a method of producing a neuron MOS transistor in which the necessary coupling capacitances are obtained either via capacitors with a similar structure to transistors or via transfer gates of a CMOS standard process arranged as capacitors. A substantial advantage is the great compatibility of the process with a standard CMOS process.