HALBLEITERNEURON MIT VARIABLEN EINGANGSGEWICHTEN
    4.
    发明公开
    HALBLEITERNEURON MIT VARIABLEN EINGANGSGEWICHTEN 失效
    半导体EURON变量输入权系数

    公开(公告)号:EP0876681A1

    公开(公告)日:1998-11-11

    申请号:EP96946149.0

    申请日:1996-12-18

    CPC classification number: H01L29/7881 G06N3/0635

    Abstract: The invention concerns a semiconductor neuron in which input electrodes are coupled capacitively to a floating gate (FG) of which the potential controls the current of a MOSFET (NT), and in which a respective neuron input (E1 ... E4) can be connected to partial electrodes (1 ... 7) of a respective input electrode such that the entire surface of the partial electrodes connected to the respective neuron input corresponds to a respective weight of the neuron input. The invention combines the high processing speed of a hardware neuron with the flexibility of a software neuron.

    SCHALTUNGSANORDNUNG ZUM VERGLEICH ZWEIER ELEKTRISCHER GRÖSSEN
    5.
    发明公开
    SCHALTUNGSANORDNUNG ZUM VERGLEICH ZWEIER ELEKTRISCHER GRÖSSEN 失效
    电路出于比较的两个电动尺码

    公开(公告)号:EP0834116A1

    公开(公告)日:1998-04-08

    申请号:EP96915961.0

    申请日:1996-06-03

    CPC classification number: G06F7/53 G06F2207/4826

    Abstract: The invention relates to a circuit by means of which two electrical quantities in the form of a first transverse current (I1) and a second transverse current (I2) can be mutually compared. The circuit has a first inverter stage (n1, p1). An output (50, 51) of the two inverter stages (n1, p1, n2, p2) are coupled to an input of the other inverter stage (52, 53). Between the two outputs of the two inverter stages (n1, p2) there is a reset unit (5) which, on being activated, starts the current comparison. If the reset unit (5) is deactivated, the output datum obtained during the evaluation remains stable.

    MAGNETORESISTIVER SPEICHER MIT ERHÖHTER STÖRSICHERHEIT
    8.
    发明公开
    MAGNETORESISTIVER SPEICHER MIT ERHÖHTER STÖRSICHERHEIT 有权
    具有增强抗干扰磁阻存储器

    公开(公告)号:EP1119860A2

    公开(公告)日:2001-08-01

    申请号:EP99969820.2

    申请日:1999-09-29

    CPC classification number: G11C11/16 H01L27/222

    Abstract: The invention relates to a magnetoresistive memory having improved interference immunity while keeping the chip surface small. Interference immunity is improved by arranging word lines vertically between two complementary bit lines. Also, a magnetoresistive memory system of a regular cell is provided between a bit line and a word line, and a pertaining magnetoresistive layer system of a complementary memory cell is provided between the complementary bit line and the word line.

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