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公开(公告)号：EP0329125A3
公开(公告)日：1993-05-26
申请号：EP89102628.8
申请日：1989-02-16
CPC分类号： G01D5/24476 , G01D3/08 , G01D5/24404
摘要： Die Schaltungsanordnung gemäß Figur 1 weist zur Synchronisierung von Rechtecksignalfolgen (RO... Rk) eine Synchronisierungs-Baueinheit (1) auf. Durch Störimpulse, die im Vorfeld der Synchronisierungs-Baueinheit (1) auftreten können, kann es zu fehlerhaften Ausgangssignalen kommen. Ein digital arbeitendes Filter (DF), welches der Synchronisierungs-Baueinheit (1) vorgeschaltet ist, verhindert, daß fehlerhafte Signalkombinationen in Form von unzulässigen Bit-Mustern an die Eingänge der Synchronisierungs-Baueinheit (1) gelangen. Das digital arbeitende Filter (DF) besteht aus einem getakteten Adreßregister (AR) und einem Speicher (S), der für jedes mögliche Bit-Muster der Rechtecksignalfolgen (RO...Rk) eine Speicherzelle (Si) aufweist. Die einzelne Speicherzelle (Si), die entsprechend dem momentanen Bit-Muster adressiert wird, enthält die Information, ob das momentane Bit-Muster zulässig oder unzulässig ist.
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公开(公告)号：EP0328683B1
公开(公告)日：1993-03-03
申请号：EP88907359.9
申请日：1988-08-19
申请人： FANUC LTD.
IPC分类号： G01D5/245
CPC分类号： H03M1/303 , G01D5/24404 , G01D5/24409
摘要： An apparatus for processing signals of a pulse encoder electrically processes output signals from a signal generator to improve the resolution of the encoder. Sine wave signals and cosine wave signals supplied from the signal generator are converted into digital signals through first and second A/D converters, respectively, and are supplied to a signal conversion means which produces an analog amplitude level and position data depending upon the outputs of the first and second A/D converters. Thus, the circuit constitution ca be simplified, the space occupied by the apparatus can be reduced, and the intensity of signals supplied from the signal source can be confirmed.
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公开(公告)号：EP0293479B1
公开(公告)日：1992-06-03
申请号：EP87907147.0
申请日：1987-11-02
申请人： FANUC LTD.
IPC分类号： G01D5/245
CPC分类号： G01D5/24457 , G01D5/24404 , H03M1/1076 , H03M1/303
摘要： A pulse encoder having a movement detecting unit (1) that detects the movement of an object whose position is to be detected and produces a signal having data related to the movement, and a clock generator (3) that produces clock pulses. The data related to the movement is processed while maintaining synchronism with the clock pulses. Provision is further made of an abnormal clock detecting unit (4) which inputs clock pulses as well as portions having data that indicates the presence or absence of movement of the object whose position should at least be detected among the signals having data related to the movement. When the movement is detected relying upon portions having data that indicates the presence or absence of movement despite the interruption of the clock pulse, the abnormal clock detecting unit (4) produces an abnormal clock signal.
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公开(公告)号：EP0320596B1
公开(公告)日：1992-05-27
申请号：EP88117227.4
申请日：1988-10-17
发明人： Schwefel, Ernst, Dipl.-Phys. , Schmitt, Walter, Ing.(Grad.) , 1Huber, Norbert, Dipl.-Ing. (FH) , Lengenfelder, Hans, Dipl.-Ing. (FH)
IPC分类号： G01D5/26
CPC分类号： H03M1/203 , G01D5/24404 , H03M1/303
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公开(公告)号：EP0199826B1
公开(公告)日：1992-04-22
申请号：EP85905437.1
申请日：1985-11-05
申请人： FANUC LTD.
发明人： SAKANO, Tetsuro
CPC分类号： G01D5/24409 , G01D5/24404 , H03M1/30
摘要： A method of detecting a position comprising a step for generating two sinusoidal wave signals having phases that are spacially different by 90o, corresponding to movement of a moving body; a step which detects voltages Va, Vb of the two sinusoidal wave signals to calculate a value alpha which makes the value V = Va.cos alpha - Vb.sin alpha zero; a step which so determines the value alpha that signs of sin alpha, cos alpha for said calculated alpha agree with signs of said voltages Va, Vb respectively; and a step for detecting a position to which the moving body has moved by using the determined value alpha as data on an absolute position of the body in a cycle of said two phase signals. According to the above method of detecting a position, an absolute position of a moving body can be detected with high resolution.
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公开(公告)号：EP0207284B1
公开(公告)日：1991-09-18
申请号：EP86107105.8
申请日：1986-05-26
CPC分类号： G01D5/24404 , G01B7/00
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公开(公告)号：EP0328683A4
公开(公告)日：1991-03-13
申请号：EP88907359
申请日：1988-08-19
申请人： FANUC LTD
CPC分类号： H03M1/303 , G01D5/24404 , G01D5/24409
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公开(公告)号：EP0414953A1
公开(公告)日：1991-03-06
申请号：EP89116155.6
申请日：1989-09-01
CPC分类号： H03M1/645 , G01D5/24404
摘要： There are provided an absolute position detector (10) for sampling and outputting a digital value of absolute position data of an object of detection at each predetermined sampling timing and an interpolation circuit (22) for interpolating between position data of different sampling timings provided by the absolute position detector (10) thereby to produce absolute position data at close intervals. By this arrangement, absolute position data can be produced with a time resolution which is finer than the period of the sampling timing. There may be provided further a circuit (29) for producing an incremental pulse train on the basis of the output of the interpolation circuit (22) in correspondence to change in a value of interpolation for each interpolation step.
摘要翻译： 提供了一种绝对位置检测器（10），用于在每个预定采样定时对采样和输出检测对象的绝对位置数据的数字值进行输出;以及内插电路（22），用于内插不同采样定时的位置数据 绝对位置检测器（10），从而以紧密的间隔产生绝对位置数据。 通过这种布置，可以以比采样定时的周期更精细的时间分辨率来产生绝对位置数据。 可以提供另外一个电路（29），用于根据内插电路（22）的输出，根据每个内插步骤的内插值的变化产生增量脉冲串。
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29.发明公开Schaltungsanordnung zur Erkennung von Störsignalen 失效Schaltungsanordnung zur Erkennung vonStörsignalen。
公开(公告)号：EP0329125A2
公开(公告)日：1989-08-23
申请号：EP89102628.8
申请日：1989-02-16
CPC分类号： G01D5/24476 , G01D3/08 , G01D5/24404
摘要： Die Schaltungsanordnung gemäß Figur 1 weist zur Synchronisierung von Rechtecksignalfolgen (RO... Rk) eine Synchronisierungs-Baueinheit (1) auf. Durch Störimpulse, die im Vorfeld der Synchronisierungs-Baueinheit (1) auftreten können, kann es zu fehlerhaften Ausgangssignalen kommen. Ein digital arbeitendes Filter (DF), welches der Synchronisierungs-Baueinheit (1) vorgeschaltet ist, verhindert, daß fehlerhafte Signalkombinationen in Form von unzulässigen Bit-Mustern an die Eingänge der Synchronisierungs-Baueinheit (1) gelangen. Das digital arbeitende Filter (DF) besteht aus einem getakteten Adreßregister (AR) und einem Speicher (S), der für jedes mögliche Bit-Muster der Rechtecksignalfolgen (RO...Rk) eine Speicherzelle (Si) aufweist. Die einzelne Speicherzelle (Si), die entsprechend dem momentanen Bit-Muster adressiert wird, enthält die Information, ob das momentane Bit-Muster zulässig oder unzulässig ist.
摘要翻译： 根据图1的电路装置展示了用于同步方波信号序列（RO ... Rk）的同步模块（1）。 输出信号可能由同步模块（1）的输入端产生的干扰脉冲产生。 在同步模块（1）之前的数字滤波器（DF）防止以不允许的位模式的形式的错误信号组合到达同步模块（1）的输入。 数字滤波器（DF）包括时钟地址寄存器（AR）和存储器（S），其具有用于方波信号序列（RO ... Rk）的每个可能位模式的一个存储单元（Si）。 根据瞬时位模式寻址的单个存储单元（Si）包含瞬时位模式是可接受还是不可接受的信息。
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公开(公告)号：EP0293479A1
公开(公告)日：1988-12-07
申请号：EP87907147.0
申请日：1987-11-02
申请人： FANUC LTD
IPC分类号： G01D5/245
CPC分类号： G01D5/24457 , G01D5/24404 , H03M1/1076 , H03M1/303
摘要： A pulse encoder having a movement detecting unit (1) that detects the movement of an object whose position is to be detected and produces a signal having data related to the movement, and a clock generator (3) that produces clock pulses. The data related to the movement is processed while maintaining synchronism with the clock pulses. Provision is further made of an abnormal clock detecting unit (4) which inputs clock pulses as well as portions having data that indicates the presence or absence of movement of the object whose position should at least be detected among the signals having data related to the movement. When the movement is detected relying upon portions having data that indicates the presence or absence of movement despite the interruption of the clock pulse, the abnormal clock detecting unit (4) produces an abnormal clock signal.
摘要翻译： 没有更多的信息。
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