Abstract:
An electronic device includes a frequency variable circuit 15, a filter 16, and an output voltage decision circuit 17. The frequency variable circuit 15 changes the sampling frequency of an analog-digital converter 13. The filter 16 limits the pass band of the output signal of the analog-digital converter 13. The output voltage decision circuit 17 determines the noise level of the output signal of the analog-digital converter 13 after the output signal passes through the filter 16. The electronic device performs self-diagnosis as follows. The frequency variable circuit 15 changes the sampling frequency of the analog-digital converter 13 to a frequency outside of the pass band of the filter 16 so as to change the quantization noise level of the analog-digital converter 13. Then, the output voltage decision circuit 17 determines whether the integral of the quantization noise level is within a predetermined range.
Abstract:
An analog-to-digital converter, ADC, system (200) configured to receive a first (V1) and a second (V2) analog quantity and to provide a plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities. The ADC system includes a first (301), a second (302), and a third (305) ADC circuit, and a digital interface circuit (303). The first ADC circuit (301) is configured to provide a first code (D1) representative of the first analog quantity (V1) and to provide a first analog residue quantity (R1) representative of the first analog quantity (V1) with respect to the first code (D1). The second ADC circuit (302) is configured to provide a second code (D2) representative of the second analog quantity (V2) and to provide a second analog residue quantity (R2) representative of the second analog quantity (V2) with respect to the second code (D2). The third ADC circuit (304) is configured to receive the first (R1) and second (R2)analog residue quantities, and to provide a third digital code (D3) representative of a difference of the first (R1) and second (R2) analog residue quantities. The digital interface circuit (303) is configured to receive the first (D1), second (D2), and third (D3) codes, and to provide the plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities.
Abstract:
An encoder device comprising an encoding means (10) and a detector (20,40) which are movable relative to one another, the detector (20,40) being adapted to generate at least one pulse signal (A di ) whose amplitude changes with relative positional changes; the encoder further comprising:
a load sensor (42; 180) having an input coupled to receive the at least one pulse signal, and an output for delivering an output signal (A do ); wherein the encoder device comprises means for indicating when the sensed load exceeds a threshold level.
Abstract:
Bei einer Schaltungsanordnung zur Kontrolle einer Ausgangslast (4) eines Strom-Digital-Analog-Konverters (1), der in Abhängigkeit eines digitalen Datenwortes einen analogen Ausgangsstrom liefert, welcher einem ersten Widerstand (2) und gegebenenfalls der diesem parallelgeschalteten Ausgangslast (4) zugeführt wird, ist für eine mögliche laufende Kontrolle der Ausgangslast vorgesehen, daß ein erster, digitaler Komparator (12) vorgesehen ist, welcher die dem Strom-Digital-Analog-Konverter (1) zugeführten Datenworte mit wenigstens einem Vergleichs-Datenwort vergleicht, daß ein zweiter, analoger Komparator (5) vorgesehen ist, welcher die über dem ersten Widerstand (2) abfallende Spannung mit wenigstens einer Referenzspannung vergleicht und dessen Ausgangssignal einem Flip-Flop (8) zugeführt wird, und daß eine Vergleichsschaltung (11) vorgesehen ist, welche In Abhängigkeit der Ausgangssignale des ersten Komparators (12) und des Flip-Flops (8) eine Kontrolle der Größe und/oder der Existenz der Ausgangslast (4) vornimmt.
Abstract:
Each slit track of the disk of an optical type absolute encoder are divided into a group corresponding to an area to which a LED can emit light. A reference track of only a transparent portion is provided in this group. In the case of converting a detection signal into square waves, the detection signal is converted into a square wave output by using the output signal of the reference track as an index.
Abstract:
Each slit track of the disk of an optical type absolute encoder are divided into a group corresponding to an area to which a LED can emit light. A reference track of only a transparent portion is provided in this group. In the case of converting a detection signal into square waves, the detection signal is converted into a square wave output by using the output signal of the reference track as an index.
Abstract:
Die Erfindung betrifft einen Hydraulikzylinder für eine landwirtschaftliche Arbeitsmaschine (2) mit einer Zylindereinheit (3) und einem in der Zylindereinheit über eine Hublänge laufenden Kolben (3) mit einer geometrischen Kolbenlängsachse, wobei der Kolben durch in die Zylindereinheit eingeleiteten Hydraulikdruck antreibbar ist, wobei sich zum Ausleiten von Antriebskraft von dem Kolben eine Kolbenstange (7) durch die Zylindereinheit hindurch erstreckt, wobei an der Zylindereinheit eine optische Messanordnung (16) vorgesehen ist und wobei an der Kolbenstange mindestens eine Messmarkierung (17) vorgesehen ist, die bei einer Verstellung der Kolbenstange an der Messanordnung vorbeiläuft und von der Messanordnung zur Ermittlung der Kolbenstellung erfassbar ist. Es wird vorgeschlagen, dass die Messmarkierung durch die Wärmebehandlung des Anlassens, insbesondere Laseranlassens, an der Oberfläche der Kolbenstange erzeugt ist und dass die Messanordnung in einem Bereich angeordnet ist, der frei von dem in der Zylindereinheit jeweils wirkenden Hydraulikdruck ist.
Abstract:
An analog-to-digital converter, ADC, system (200) configured to receive a first (V1) and a second (V2) analog quantity and to provide a plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities. The ADC system includes a first (301), a second (302), and a third (305) ADC circuit, and a digital interface circuit (303). The first ADC circuit (301) is configured to provide a first code (D1) representative of the first analog quantity (V1) and to provide a first analog residue quantity (R1) representative of the first analog quantity (V1) with respect to the first code (D1). The second ADC circuit (302) is configured to provide a second code (D2) representative of the second analog quantity (V2) and to provide a second analog residue quantity (R2) representative of the second analog quantity (V2) with respect to the second code (D2). The third ADC circuit (304) is configured to receive the first (R1) and second (R2)analog residue quantities, and to provide a third digital code (D3) representative of a difference of the first (R1) and second (R2) analog residue quantities. The digital interface circuit (303) is configured to receive the first (D1), second (D2), and third (D3) codes, and to provide the plurality of numerical parameters (CODE) representative of the first (V1) and second (V2) analog quantities.