公开(公告)号：EP2012250A2

公开(公告)日：2009-01-07

申请号：EP08103649.3

申请日：2008-04-22

Applicant: Siemens AG Österreich

Inventor： Hallak, Jalal

IPC: G06G7/16

CPC classification number: G06G7/16 ,  G06G7/161

Abstract: Die Erfindung betrifft einen Verfahren zum Betreiben eines Analog Dividierers, wobei ein Sägezahn- oder Dreieckssignal aus einer erste Eingangsspannung (U1) als Divisor gebildet wird, und wobei dieses Sägezahn- oder Dreieckssignal mittels eines ersten Komparators (KO1) mit einer zweiten Eingangsspannung (U2) als Dividend in der Weise verglichen wird, dass als ein erstes Vergleichssignal (SIG1 OUT ) ein pulsweitenmoduliertes Signal erzeugt wird, dessen Mittelwert als Quotienten der Division ausgegeben wird. Dabei wird das Sägezahn- oder Dreieckssignal mittels eines ersten und eines zweiten Reglers (REG1, REG2) gebildet und dem ersten Regler (REG1) die erste Eingangsspannung (U1) oder eine dazu proportionale Spannung und das Sägezahn- oder Dreieckssignal oder ein dazu proportionales Signal in der Weise zugeführt, dass der obere Spitzenwert des Sägezahn- oder Dreieckssignals der ersten Eingangsspannung nachgeregelt wird. Des Weiteren wird dem zweiten Regler (REG2) das Bezugspotenzial und das Sägezahn- oder Dreieckssignal in der Weise zugeführt, dass der untere Spitzenwert des Sägezahn- oder Dreieckssignals dem Wert des Bezugspotenzials nachgeregelt wird.

Abstract translation: 该方法包括通过比较器（KO1）将锯齿或三角形信号与输入电压（U2）进行比较，使得产生脉冲宽度调制信号作为比较信号（SIG1out）。 三角形信号的输入电压（U1）或与电压（U1）成比例的电压和信号被提供给控制器（REG1），使得三角形信号的上峰值被重新调整。 将参考电位和三角形信号提供给另一控制器（REG2），使得三角形信号的较低峰值被重新调整为电位值。 对于具有锯齿或三角形信号发生器的模拟分频器也包括独立权利要求。

公开(公告)号：EP1872297A2

公开(公告)日：2008-01-02

申请号：EP06733075.3

申请日：2006-04-24

Applicant: SiTel Semiconductor B.V.

Inventor： NIJROLDER, Manjo

IPC: G06G7/16

CPC classification number: H03D7/1441 ,  G06G7/16 ,  H03D7/1458 ,  H03D2200/0033 ,  H03D2200/0084

Abstract: A current mode multiplier circuit is provided based on the square root voltage-current relationship of an MOS transistor. The circuit includes first, second and third MOS transistors with a common aspect ratio, and first and second current sources that respectively provide first and second input currents that represent first and second factors to be multiplied. The first and second MOS transistors produce first and second voltages as a function of the first and second input currents, and the third MOS transistor produces a third current as a function of the first and second voltages. In response to the third current, the circuit produces a product signal that represents a product of the first and second factors.

公开(公告)号：EP0807898A3

公开(公告)日：1998-06-17

申请号：EP97107745

申请日：1997-05-12

Applicant: SIEMENS AG

Inventor： WEBER STEPHAN

IPC: G06G7/16

CPC classification number: G06G7/16

Abstract: Schaltungsanordnung zur Parametereinstellung mit mindestens einer ersten analogen Multipliziereinrichtung (1, 2, 3), der ein Eingangssignal (17, 18, 19) sowie ein einem Parameter entsprechendes Steuersignal zugeführt wird und die ein Ausgangssignal (20, 21, 22) abgibt,
mit einer zur ersten Multiplikationseinrichtung (1, 2, 3) identischen zweiten Multiplikationseinrichtung (25), der ein erstes Referenzsignal sowie ein dem ersten Steuersignal entsprechendes zweites Steuersignal zugeführt werden und die ein Ausgangssignal (Ui) abgibt, und mit einer Regeleinrichtung (38 bis 45), die das Ausgangssignal (Ui) der zweiten Multipliziereinrichtung (25) mit einem zweiten Referenzsignal (Us) vergleicht und daraus die Steuersignale ableitet.

公开(公告)号：EP3286762A4

公开(公告)日：2018-04-18

申请号：EP16891824

申请日：2016-02-25

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： BUCHANAN BRENT ,  ZHENG LE

IPC: G11C11/16 ,  G06G7/16 ,  G11C7/10 ,  G11C11/54 ,  G11C13/00 ,  H01L43/08

CPC classification number: G11C7/1006 ,  G06G7/16 ,  G11C11/54 ,  G11C13/0002

Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

公开(公告)号：EP3286762A1

公开(公告)日：2018-02-28

申请号：EP16891824

申请日：2016-02-25

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： BUCHANAN BRENT ,  ZHENG LE

IPC: G11C11/16 ,  G11C13/00 ,  H01L43/08

CPC classification number: G11C7/1006 ,  G06G7/16 ,  G11C11/54 ,  G11C13/0002

Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.

公开(公告)号：EP3267355A1

公开(公告)日：2018-01-10

申请号：EP17177059.7

申请日：2017-06-21

Applicant: Hewlett Packard Enterprise Development LP

Inventor： MURALIMANOHAR, Naveen ,  FEINBERG, Ben ,  SHAFIEE-ARDESTANI, Ali

IPC: G06G7/16

CPC classification number: G06F17/16 ,  G06G7/16 ,  H03M1/12 ,  H03M1/66

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

Abstract translation: 这里的例子涉及用于计算涉及负值的向量 - 矩阵乘法的电路。 第一存储器交叉开关阵列可以被映射到包括输入矩阵的正值的第一矩阵。 第二存储器交叉开关阵列可以被映射到包括输入矩阵的负值的第二矩阵。 模数转换器可以基于由存储器交叉开关阵列计算的模拟结果来生成数字中间乘法结果。 数字中间乘法结果可以包括与第一矢量和第二矢量中的每一个与第一矩阵和第二矩阵中的每一个相乘的中间结果。 控制器可以聚集数字中间结果以产生组合的多个结果，其表示输入矢量和输入矩阵的矢量矩阵相乘。

公开(公告)号：EP3234947A1

公开(公告)日：2017-10-25

申请号：EP14908534.2

申请日：2014-12-15

Applicant: Hewlett Packard Enterprise Development LP

Inventor： GE, Ning ,  YANG, Jianhua ,  STRACHAN, John Paul ,  HU, Miao

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

Abstract translation: 在一个例子中提供非易失性存储器交叉阵列。 所述阵列包括：由与多个列线交叉的多个行线形成的多个结; 在耦合在第一组行线和第一组列线之间的第一组结点处的第一组控制; 在耦合在第二组行线和第二组列线之间的第二组结点处的第二组控制; 以及电流收集线，用于通过第一组和第二组的控制线通过它们各自的列线收集电流，并输出对应于第一点积和第二点积的和的结果电流。

公开(公告)号：EP3221864A1

公开(公告)日：2017-09-27

申请号：EP14906359.6

申请日：2014-11-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： STRACHAN, John Paul ,  MONTGOMERY, Glen E. ,  GE, Ning ,  HU, Miao ,  YANG, Jianhua

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G01J1/00 ,  G06G7/16 ,  G11C7/062 ,  G11C7/067 ,  G11C7/1006 ,  G11C11/1673 ,  G11C13/0021 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2013/0088 ,  G11C2213/77

Abstract: A method of obtaining a dot product using a memristive dot product engine with a nulling amplifier includes applying a number of programming voltages to a number of row lines within a memristive crossbar array to change the resistance values of a corresponding number of memristors located at intersections between the row lines and a number of column lines. The method also includes applying a number of reference voltages to the number of the row lines and applying a number of operating voltages to the number of the row lines. The operating voltages represent a corresponding number of vector values. The method also includes determining an array output based on a reference output and an operating output collected from the number of column lines.

Abstract translation: 使用具有归零放大器的忆阻点积产品引擎来获得点积的方法包括：将多个编程电压施加到忆阻式交叉开关阵列内的多个行线以改变位于交叉点之间的交点处的对应数目的忆阻器的电阻值 行线和一些列线。 该方法还包括将多个参考电压施加到多条行线并将多个工作电压施加到多条行线。 工作电压表示相应数量的矢量值。 该方法还包括基于从多个列线收集的参考输出和操作输出来确定阵列输出。

公开(公告)号：EP2339500A2

公开(公告)日：2011-06-29

申请号：EP10195124.2

申请日：2010-12-15

Applicant: Macroblock, Inc.

Inventor： Shih, Fu-Yang

IPC: G06G7/16

CPC classification number: G06G7/16

Abstract: An analog multiplier includes a bias circuit, a level shifter, a multiplying circuit, and a current mirror. The analog multiplying circuit is used for inputting a first voltage and a second voltage, and outputting a product current. The product current is proportional to a product of the first voltage and the second voltage. The analog multiplier is implemented by a few devices, thereby having a simple architecture and being capable of being driven by a small amount of power.

Abstract translation: 模拟乘法器包括偏置电路，电平转换器，乘法电路和电流镜。 模拟乘法电路用于输入第一电压和第二电压，并输出产品电流。 产品电流与第一电压和第二电压的乘积成比例。 模拟乘法器由几个设备实现，从而具有简单的架构并且能够被少量的电力驱动。

公开(公告)号：EP0346435B1

公开(公告)日：1992-11-11

申请号：EP89900998.9

申请日：1988-12-09

Applicant: Unisys Corporation (a Delaware corp.)

Inventor： KEATE, Christopher, R.

IPC: G06G7/16

CPC classification number: H03D1/2272 ,  G06G7/16

Abstract: A high-speed analog multiplier circuit (Figs. 3-6) for multiplying two analog inputs (X, Y) comprises a signum generator (21) having an X input multiplier (at 26, 27) and having an output connected to a high-speed electronic switch (22). A Y analog input multiplicand (at 28) is also connected to the high-speed electronic switch (22) and the output of the electronic switch (32, 33) having a positive input (33), a negative input (32) and a resultant output (24) for producing the signum function (X) times Y. The electronic switch (22) is operated by the signum generator (21) so that the presence of a high Q output from the signum generator (21) is effective to connect the Y multiplicand input (28) to the positive input (33) of the differential amplifier (23) and that the presence of a high Q input (27) from the signum generator (21) is effective to connect the Y multiplicand input (28) to the negative input (32) of the differential amplifier (23).