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    SINE WAVE MULTIPLICATION DEVICE AND INPUT DEVICE HAVING SAME
    2.
    发明公开
    SINE WAVE MULTIPLICATION DEVICE AND INPUT DEVICE HAVING SAME 审中-公开
    正弦波乘法装置和具有该装置的输入装置

    公开(公告)号：EP3285395A1

    公开(公告)日：2018-02-21

    申请号：EP16779937.8

    申请日：2016-04-01

    申请人： Alps Electric Co., Ltd.

    发明人： FUJIYOSHI, Tatsumi ,  SAGAWAI, Shinichi ,  SASAI, Kiyoshi

    IPC分类号： H03D7/00 ,  H03H19/00

    CPC分类号： G06F7/548 ,  G06G7/16 ,  H03D7/1425 ,  H03D7/1466 ,  H03D7/1483 ,  H03D2200/006 ,  H03D2200/0074 ,  H03D2200/0086

    摘要： Provided is a sine wave multiplication device of simple configuration, broad input signal level range, and minimal fluctuation in characteristics due to temperature. A signal component that corresponds to a product of an input signal Si and the third harmonic wave of a first square wave W1 included in an output signal Su1; and a signal component that corresponds to a product of the input signal Si and the fifth harmonic wave of the first square wave W1 is canceled by: a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W2 included in an output signal Su2; and a signal component that corresponds to a product of the input signal Si and the fundamental wave of a second square wave W3 included in an output signal Su3.

    摘要翻译： 提供了一种结构简单，输入信号电平范围宽，温度特性波动小的正弦波倍增器。 对应于包括在输出信号Su1中的输入信号Si与第一方波W1的三次谐波的乘积的信号分量; 并且对应于输入信号Si与第一方波W1的第五谐波的乘积的信号分量通过以下来抵消：与输入信号S1和第二方波的基波的乘积相对应的信号分量 包括在输出信号Su2中的波形W2; 以及对应于包括在输出信号Su3中的输入信号Si与第二方波W3的基波的乘积的信号分量。

    NONVOLATILE MEMORY CROSS-BAR ARRAY
    4.
    发明公开
    NONVOLATILE MEMORY CROSS-BAR ARRAY 审中-公开

    公开(公告)号：EP3234947A4

    公开(公告)日：2017-12-06

    申请号：EP14908534

    申请日：2014-12-15

    申请人： HEWLETT PACKARD ENTPR DEV LP

    发明人： GE NING ,  YANG JIANHUA ,  STRACHAN JOHN PAUL ,  HU MIAO

    IPC分类号： G11C13/00

    CPC分类号： G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

    摘要： Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

    Schaltungsanordnung zur Parametereinstellung
    6.
    发明公开
    Schaltungsanordnung zur Parametereinstellung 失效

    公开(公告)号：EP0807898A2

    公开(公告)日：1997-11-19

    申请号：EP97107745.8

    申请日：1997-05-12

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Weber, Stephan

    IPC分类号： G06G7/16

    CPC分类号： G06G7/16

    摘要： Schaltungsanordnung zur Parametereinstellung mit mindestens einer ersten analogen Multipliziereinrichtung (1, 2, 3), der ein Eingangssignal (17, 18, 19) sowie ein einem Parameter entsprechendes Steuersignal zugeführt wird und die ein Ausgangssignal (20, 21, 22) abgibt,
    mit einer zur ersten Multiplikationseinrichtung (1, 2, 3) identischen zweiten Multiplikationseinrichtung (25), der ein erstes Referenzsignal sowie ein dem ersten Steuersignal entsprechendes zweites Steuersignal zugeführt werden und die ein Ausgangssignal (Ui) abgibt, und mit einer Regeleinrichtung (38 bis 45), die das Ausgangssignal (Ui) der zweiten Multipliziereinrichtung (25) mit einem zweiten Referenzsignal (Us) vergleicht und daraus die Steuersignale ableitet.

    摘要翻译： 每个由发射极耦合晶体管（例如4,5）的差分放大器组成的三个模拟倍增级（1-3）在每对的一个晶体管的基极处接收相应的输入信号（17-19），而另一个的基极 接地（23）。 另一个乘法级（25）被相同地构造成从源极（40）和电位分配器（41,42）接收第一参考信号。 将该级的输出与第二参考信号（Us）进行比较（38）。 比较的结果用于导出所有级的耦合的发射极电路中的电流组输出晶体管（28-34）的控制信号。

    An inner product calculation device
    7.
    发明公开
    An inner product calculation device 失效
    Einrichtung zur Berechnung von Skalarprodukten

    公开(公告)号：EP0727751A1

    公开(公告)日：1996-08-21

    申请号：EP96102020.3

    申请日：1996-02-12

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Iizuka, Kunihiko ,  Fujio, Mitsuhiko ,  Matsui, Hirofumi ,  Miyamoto, Masayuki

    IPC分类号： G06G7/14 ,  G06G7/16 ,  G06J1/00

    CPC分类号： G06J1/005 ,  G06G7/14 ,  G06G7/16

    摘要： An inner product calculation device for calculating an inner product of a coefficient vector including at least one first element with a positive sign and at least one second element with a negative sign and an input vector including elements corresponding to a plurality of input voltages according to the present invention includes: an amplifier having an input terminal and an output terminal; at least one first capacitor corresponding to the first element, the first capacitor including one end, another end, and a capacitance in proportion to a value of the first element; at least one second capacitor corresponding to the second element, the second capacitor including one end, another end, and a capacitance in proportion to an absolute value of the second element; a third capacitor having one end and another end, the one end of the third capacitor being connected to the one end of the first capacitor, the one end of the second capacitor, and the input terminal of the amplifier; a voltage source for: (a) applying, during a first period, a corresponding one of the input voltages to the other end of each first capacitor and a reference voltage to the other end second capacitor and the other end of the third capacitor; and (b) applying, during a second period following the first period, the reference voltage to the other end of the first capacitor, a corresponding one of the plurality of input voltages to the other end of each second capacitor, and an output voltage output from the output terminal of the amplifier to the other end of the third capacitor; and a switch for short-circuiting the input terminal of the amplifier and the output terminal of the amplifier during a third period.

    摘要翻译： 一种内积计算装置，用于计算包括具有正号的至少一个第一元件和至少一个带有负号的第二元件的系数向量的内积和包括与多个输入电压对应的元素的输入向量 本发明包括：具有输入端和输出端的放大器; 至少一个对应于所述第一元件的第一电容器，所述第一电容器包括与所述第一元件的值成比例的一端，另一端和电容; 至少一个与所述第二元件对应的第二电容器，所述第二电容器包括与所述第二元件的绝对值成比例的一端，另一端和电容; 具有一端和另一端的第三电容器，第三电容器的一端连接到第一电容器的一端，第二电容器的一端和放大器的输入端; 电压源，用于：（a）在第一时段期间将对应的一个输入电压施加到每个第一电容器的另一端，并将参考电压施加到另一端第二电容器和第三电容器的另一端; 以及（b）在所述第一周期之后的第二时段期间将所述参考电压施加到所述第一电容器的另一端，将所述多个输入电压中的对应一个输入到每个第二电容器的另一端，以及输出电压输出 从放大器的输出端子到第三电容器的另一端; 以及用于在第三时段内使放大器的输入端和放大器的输出端短路的开关。

    HIGH-SPEED ANALOG MULTIPLIER - ABSOLUTE VALUE DETECTOR
    8.
    发明公开
    HIGH-SPEED ANALOG MULTIPLIER - ABSOLUTE VALUE DETECTOR 失效
    FAST模拟乘法器绝对检测。

    公开(公告)号：EP0346435A1

    公开(公告)日：1989-12-20

    申请号：EP89900998.0

    申请日：1988-12-09

    申请人： Unisys Corporation (a Delaware corp.)

    发明人： KEATE, Christopher, R.

    IPC分类号： G06G7 ,  H03D1

    CPC分类号： H03D1/2272 ,  G06G7/16

    摘要： A high-speed analog multiplier circuit (Figs. 3-6) for multiplying two analog inputs (X, Y) comprises a signum gen­ erator (21) having an X input multiplier (at 26, 27) and having an output connected to a high-speed electronic switch (22) A Y analog input multiplicand (at 28) is also connected to the high-speed electronic switch (22) and the output of the elec­ tronic switch (32, 33) having a positive input (33), a negative input (32) and a resultant output (24) for producing the sign­ num function (X) times Y. The electronic switch (22) is operated by the signum generator (21) so that the presence of a high Q output from the signum generator (21) is effective to connect the Y multiplicand input (28) to the positive input (33) of the differential amplifier (23) and that the presence of a high Q input (27) from the signum generator (21) is effective to connect the Y multiplicand input (28) to the negative input (32) of the differential amplifier (23).

    A divider circuit arrangement and a dual branch receiver having such a divider circuit arrangement
    9.
    发明公开
    A divider circuit arrangement and a dual branch receiver having such a divider circuit arrangement 失效
    Teilerschaltungseinrichtung undDoppelzweigempfängermit einer solchen Teilerschaltungseinrichtung。

    公开(公告)号：EP0315268A2

    公开(公告)日：1989-05-10

    申请号：EP88202427.6

    申请日：1988-10-31

    申请人： Philips Electronics N.V.

    发明人： Chung, Kah-Seng

    IPC分类号： G06G7/16

    CPC分类号： G06G7/16

    摘要： A divider circuit arrangement in which in order to avoid dividing by zero the divisor (V d ) is modified by the addition of an extra signal (X a ) to form a modified divisor V′ d = V d + X a and the dividend (V i ) is modified by the addition of the product of the quotient (V o ) and the extra signal (X a ) to form a modified dividend V′ i = V i + V o X a .
    A particular but not exclusive application of this divider circuit arrangement is in normalising an output signal from a dual branch receiver (not shown).

    摘要翻译： 一种除法器电路装置，为了避免除数除数（Vd），通过添加额外的信号（Xa）来修改，以形成修正除数V min d = Vd + Xa，并且除数（Vi）被修改 通过添加商（Vo）和额外信号（Xa）的乘积以形成修改的分红V min i = Vi + VoXa。 该分频器电路装置的一个特殊的但并不排他的应用是将来自双分支接收器（未示出）的输出信号归一化。