公开(公告)号：EP4256630B1

公开(公告)日：2024-05-15

申请号：EP21801518.8

申请日：2021-10-27

IPC: H10N70/20 ,  H03K19/21

CPC classification number: G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/00820130101 ,  H10N70/8613 ,  H10N70/231 ,  H10N70/8828 ,  H03K19/21

公开(公告)号：EP4354436A1

公开(公告)日：2024-04-17

申请号：EP23187989.1

申请日：2023-07-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Gopinath, Venkatesh P. ,  Parvarandeh, Pirooz

IPC: G11C7/10 ,  G06F7/544 ,  G06N3/065 ,  G11C7/12 ,  G11C11/54 ,  G11C11/56 ,  G11C13/00 ,  G11C27/02

CPC classification number: G11C7/1006 ,  G06F7/5443 ,  G06N3/065 ,  G11C11/54 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C7/1084 ,  G11C7/12 ,  G11C27/026 ,  G11C2213/7720130101 ,  G11C7/1039

Abstract: A structure for in-memory processing includes memory banks arranged in columns and rows, each bank having bank input nodes, at least one bitline, and cells arranged in a column and connected to corresponding bank input nodes, respectively, and to the bitline(s). Each cell includes layer-specific memory elements, which are individually programmable to store layer-specific weight values and individually connectable (e.g., by switches) to the corresponding bank input node and the bitline(s). The initial memory banks in each row also include track-and-hold devices (THs) connected to the bank input nodes. For each iteration of in-memory processing, the outputs from one processing layer are feedback to pre-designated THs for use as inputs for the next processing layer, the appropriate layer-specific memory elements in the cells are connected to the corresponding bank input nodes and bitline(s), and output(s) for the next processing layer are generated.

公开(公告)号：EP3371810A1

公开(公告)日：2018-09-12

申请号：EP16862719.8

申请日：2016-10-25

Applicant: Micron Technology, Inc.

Inventor： TORTORELLI, Innocenzo ,  TANG, Stephen ,  PAPAGIANNI, Christina

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/005 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2213/76 ,  G11C2213/77

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

公开(公告)号：EP3259756A4

公开(公告)日：2018-06-27

申请号：EP15894481

申请日：2015-06-05

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： BUCHANAN BRENT ,  GE NING ,  AULETTA RICHARD JAMES

IPC: G11C11/15 ,  G11C13/00

CPC classification number: G11C7/24 ,  G11C5/06 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2029/5002 ,  H02H1/0061 ,  H02H9/046

Abstract: In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.

公开(公告)号：EP3207575A4

公开(公告)日：2018-06-20

申请号：EP15850788

申请日：2015-10-12

Applicant: MICRON TECHNOLOGY INC

Inventor： WELLS DAVID H ,  CARDON CHRISTOPHER D ,  ONAL CANER

IPC: H01L45/00 ,  H01L45/02

CPC classification number: H01L27/2427 ,  G11C13/0007 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/33 ,  G11C2213/35 ,  G11C2213/52 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/16 ,  H01L45/1608

Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.

公开(公告)号：EP3268969A4

公开(公告)日：2018-04-11

申请号：EP15889372

申请日：2015-04-16

Applicant: HEWLETT PACKARD ENTPR DEVELOPMENT LP

Inventor： BUCHANAN BRENT

IPC: G11C13/00 ,  G11C7/10

CPC classification number: G06F17/16 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443 ,  G06F2207/4802 ,  G11C7/1006 ,  G11C13/004 ,  G11C2213/77

Abstract: In one example in accordance with the present disclosure a resistive memory array is described. The array includes a number of resistive memory elements to receive a common-valued read signal. The array also includes a number of multiplication engines to perform a multiply operation by receiving a memory element output from a corresponding resistive memory element, receiving an input signal, and generating a multiplication output based on a received memory element output and a received input signal. The array also includes an accumulation engine to sum multiplication outputs from the number of multiplication engines.

公开(公告)号：EP3281202A1

公开(公告)日：2018-02-14

申请号：EP15888693.7

申请日：2015-04-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： GE, Ning ,  YANG, Jianhua ,  HU, Miao ,  STRACHAN, John Paul

IPC: G11C11/15 ,  G11C7/04

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069

Abstract: A temperature compensation circuit may comprise a temperature sensor to sense a temperature signal of a memristor crossbar array, a signal converter to convert the temperature signal to an electrical control signal, and a voltage compensation circuit to determine a compensation voltage based on the electrical control signal and pre-calibrated temperature data of the memristor crossbar array.

公开(公告)号：EP2689423B1

公开(公告)日：2018-01-24

申请号：EP11861820.6

申请日：2011-09-16

Applicant: Toshiba Memory Corporation

Inventor： ICHIHARA, Reika ,  MATSUSHITA, Daisuke ,  FUJII, Shosuke

IPC: G11C13/00 ,  H01L27/105 ,  H01L45/00 ,  H01L49/00 ,  H01L27/10

CPC classification number: G11C13/0069 ,  G11C11/5614 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0097 ,  G11C2013/005 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/33 ,  H01L27/101 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/148

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

公开(公告)号：EP3234947A4

公开(公告)日：2017-12-06

申请号：EP14908534

申请日：2014-12-15

Applicant: HEWLETT PACKARD ENTPR DEV LP

Inventor： GE NING ,  YANG JIANHUA ,  STRACHAN JOHN PAUL ,  HU MIAO

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G06G7/16 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/79

Abstract: Provided in one example is a nonvolatile memory cross-bar array. The array includes: a number of junctions formed by a number of row lines intersecting a number of column lines; a first set of controls at a first set of the junctions coupling between a first set of the row lines and a first set of the column lines; a second set of controls at a second set of the junctions coupling between a second set of the row lines and a second set of the column lines; and a current collection line to collect currents from the controls of the first set and the second set through their respective column lines and output a result current corresponding to a sum of a first dot product and a second dot product.

公开(公告)号：EP3117435A4

公开(公告)日：2017-11-01

申请号：EP15761871

申请日：2015-03-09

Applicant: INTEL CORP

Inventor： CHU DANIEL J ,  PANGAL KIRAN ,  FRANKLIN NATHAN R ,  DAMLE PRASHANT S ,  CHAOHONG HU

IPC: G11C13/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/0061 ,  G11C2013/0047 ,  G11C2013/0052