-
公开(公告)号：EP0930573A3
公开(公告)日：2000-07-19
申请号：EP99300270.8
申请日：1999-01-15
IPC分类号： G06F13/40
CPC分类号： G06F13/409
摘要： A computer system with a SCSI backplane board has duplex-ready logic for switching the computer system between a SCSI simplex mode and a SCSI duplex mode. The duplex-ready logic includes a set of bus quick switches, a duplex-ready logic controller, and a set or sets of active terminators. The SCSI simplex mode and SCSI duplex mode are configured by the duplex-ready logic controller based on the number of SCSI cables present. If only a primary SCSI cable is present, the duplex-ready logic controller enables a SCSI simplex mode. To enable a SCSI simplex mode, the bus switches are enabled and the terminators are selectively enabled and/or disabled. If a primary SCSI cable and a secondary SCSI cable are present, the duplex-ready logic controller enables a SCSI duplex mode. To enable a SCSI duplex mode, the bus switches are disabled and the terminators are selectively disabled and/or enabled. The duplex-ready logic controller optionally may change to SCSI identification values for a set of SCSI devices for a SCSI duplex mode and restore the SCSI identification values for a SCSI simplex mode. In manually configuring the state of the SCSI backplane for the secondary SCSI duplex mode, the chassis is minimally disassembled to allow for installation of a SCSI cable from a secondary SCSI controller to the SCSI duplex-ready backplane board. The SCSI duplex-ready backplane board both eliminates the need for a board changeout and a duplex-option kit and reduces the disassembly and reassembly required to configure the state of the SCSI backplane of a computer system for a SCSI simplex mode or a SCSI duplex mode.
-
32.发明公开Computer system including a bus bridge implementing adaptive speculative read operations 审中-公开具有总线桥进行自适应推测性读操作的计算机系统
公开(公告)号：EP0924620A3
公开(公告)日：2000-06-28
申请号：EP98310413.4
申请日：1998-12-18
CPC分类号： G06F13/4059
摘要： A computer system includes a microprocessor coupled to a main memory through a bridge logic unit. The bridge logic unit receives memory read requests from the microprocessor and provides the requests to the main memory. The bridge logic unit includes a memory fetch control unit configured to fetch a single line of data from the main memory in response to an initial read request from the microprocessor. If a read request to a sequential line of data is received from the microprocessor, the memory fetch control unit fetches not only the requested line of data but also the next sequential line of data. Thus, following the initial read request in which a single line of data is fetched, when the microprocessor issues a request for data from a sequential line, that line is fetched and the subsequent line is speculatively prefetched. If the microprocessor continues with a request to yet an additional sequential line, the memory fetch unit continues its speculative generation of a request for the next sequential line. If the microprocessor issues a memory read request to a non-sequential line of data, the memory fetch control unit fetches only that line of data.
-
公开(公告)号：EP0905604A3
公开(公告)日：2000-06-21
申请号：EP98307573.0
申请日：1998-09-17
IPC分类号： G06F1/18
CPC分类号： G06F1/183
摘要： A computer system has a motherboard, a power supply and a first circuit board. The motherboard has power consuming circuitry. A first circuit board is configured to form a rigid connection with the motherboard and route power from the power supply to the motherboard through the rigid connection.
-
34.发明公开Method and apparatus for concurrent data transfer in a PCI to PCI input output processor 审中-公开一种用于在PCI-PCI输入/输出处理器同时发送数据的方法和装置
公开(公告)号：EP0917066A3
公开(公告)日：2000-05-31
申请号：EP98309097.8
申请日：1998-11-06
CPC分类号： G06F13/4027
摘要： A system for concurrent data transfer in a bus to bus input output processor including a first data path for moving data between a primary bus and a first memory, a second data path for moving data between a secondary bus and the second memory and a third data path for moving data between the primary bus, the first memory, the secondary bus, the second memory and an embedded processor. A controller controls the concurrent movement of data within the input output processor and further can convert a plurality of address lines used in the third data path for use as data lines. To effectuate the concurrent transfer of data across the various data paths, the controller isolates the embedded processor from the third data path and assigns a first destination device and a first data path to the first memory. The controller further assigns a second destination device and a second data path to the second memory. Data is then simultaneously transferred between a cache and the embedded processor, between the first memory and the first destination device across the first data path and between the second memory and the second destination device across the second data path. Data is also transferred across the primary bus to or from the input output device and across the secondary bus to or from the input output device.
-
35.发明授权APPARATUS FOR ADDING MODEM CAPABILITIES TO A COMPUTER SYSTEM EQUIPPED WITH A DIGITAL SIGNAL PROCESSOR 失效安排加入调制解调器功能一个与数字信号处理器配置的计算机系统
公开(公告)号：EP0710374B1
公开(公告)日：2000-04-19
申请号：EP94923401.7
申请日：1994-06-30
发明人： MURRAY, David, E.
CPC分类号： H04M11/06 , G06F3/162 , H04N1/00204 , H04N2201/0034
摘要： An optional card including a DSP for use by a modem daughter board, where the modem daughter board is equipped with a data access arrangement (DAA) for upgrading a computer system to include modem and facsimile capabilities. The optional card may preferably be a sound board including a DSP and bus controller for interfacing with the I/O bus of the computer system, and a CODEC and connector for receiving and interfacing the daughter board modem to the DSP. In an alternative embodiment, the DSP is provided on the system board coupled to the host bus or the I/O bus of the computer system, and the modem functions, including a CODEC and DAA, are provided on an optional modem card. The CODEC includes logic for transferring digitized analog data to main memory as controlled by the CPU of the computer system. Modem software is provided to control communications and transfer of data in any of the embodiments.
-
36.发明公开Computer expansion slot and associated logic for automatically detecting compatibility with an expansion card 审中-公开用于自动识别的计算机扩充槽和相关联的逻辑来与扩展卡的兼容性
公开(公告)号：EP0905630A3
公开(公告)日：2000-03-29
申请号：EP98307558.1
申请日：1998-09-17
IPC分类号： G06F13/40
CPC分类号： G06F13/4072
摘要： An apparatus and method for determining the types of expansion cards connected to the expansion slot connectors of a computer system. Detect signals are provided to decode logic for determining the types of expansion cards connected to the computer system. Ifthe expansion cards are compatible the decode logic produces an output power supply signal that indicates what the voltage level should be for the power supply to the cards. If the cards are incompatible, the decode logic may not provide power to any of the cards or only provide power to some ofthe cards that are compatible. For computers that allow expansion cards to connect to the computer while the computer is powered on, hot-plug logic cooperates with the decode logic to establish power and communication with newly connected interface cards. The connectors in the computer do not include keys and thus interface cards without keys, as well as cards with different types of key arrangements can be connected to and communicate with the computer. A removable keyed adapter can be mated with the expansion slot connectors to effectively provide keys to the expansion slot connectors to ensure reliable connections between the interface cards and expansion slot connectors. The adapters can be keyed in variety of arrangements to match whatever keying arrangements are included on the interface cards. In an alternative embodiment, voltage drops are provided to quick switches to ensure signaling compatibility between different card types. Further, all expansion slot connectors can be keyed for only a subset of the possible card types available and thus reduce the logic necessary to ensure compatibility.
-
公开(公告)号：EP0768607A3
公开(公告)日：2000-03-01
申请号：EP96307280.6
申请日：1996-10-04
发明人： Callison, Ryan A. , Chard, Gary F.
CPC分类号： G06F11/1076 , G06F2211/1054
摘要： Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller (118) that acts as an interface between a PCI bus (102) and a DRAM (116) that includes a write-posting cache portion (136) and an XOR buffer portion (134). The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.
-
38.发明公开Method for securely communicating remote control commands in a computer network 审中-公开在计算机网络中进行通信的远程控制命令的安全方法
公开(公告)号：EP0898216A3
公开(公告)日：2000-02-23
申请号：EP98306483.3
申请日：1998-08-14
IPC分类号： G06F1/00
CPC分类号： H04L41/28 , H04L63/0442 , H04L63/065 , H04L63/123
摘要： A method for providing secure remote control commands in a distributing computer environment. In the preferred embodiment of the invention, a network administrator or network management software creates a shutdown record, including an index or time stamp, for powering down a specified network computer(s). Prior to broadcast over the network, a secure one-way hash function is performed on the shutdown record. The result of the one-way hash function is encrypted using the network administrator's private key, thereby generating a digital signature that can be verified by specially configured network nodes. The digital signature is appended to the original shutdown record prior to broadcast to the network. Upon receiving the broadcast message, the targeted network computer(s) validates the broadcast message by verifying the digital signature of the packet or frame. The validation process is performed by decrypting the hash value representation of the shutdown record using the network administrator's public key. A one-way hash function is also performed on the original shutdown record portion of the received message. If the two values match, the broadcast message is determined to be authentic and the shutdown control code is executed. The invention insures that the shutdown command was neither modified in transit nor originated from an unauthorized source.
-
39.发明公开Method and apparatus for improved cluster administration 审中-公开Verfahren und Vorrichtung zur verb desserten Verwaltung von Gruppen
公开(公告)号：EP0962861A2
公开(公告)日：1999-12-08
申请号：EP99304353.8
申请日：1999-06-03
CPC分类号： H04L41/0893 , H04L67/42
摘要： The present inventions provide a cluster administration system that is capable of handling a cluster having one or more computing devices. The number of computing devices that may be included in a cluster is limited only by practical considerations rather than software or hardware limitations. In one embodiment, a cluster administration system includes a cluster of computing devices, one of the computing devices being an owner. The cluster further includes a resource. Direct access to the resource by the computing devices is controlled by the owner of the cluster. The cluster administration system also includes an arbiter. The arbiter and the cluster are in communication with each other and a network, the cluster providing the network with access to the storage device. The arbiter controls the admission of new computing devices to the cluster when the owner of the cluster is incapable of admitting the new computing device. Having the arbiter outside the cluster provides greater reliability. The arbiter is not affected by failures within the cluster. One or more of the computing devices of the cluster may fail, but the administration of the cluster is not affected. The functions of the arbiter may also be distributed among several independent computing devices which can hand off the primary duties of the arbiter should one or more of the independent computing devices fail to satisfactorily perform the duties of arbitration.
摘要翻译： 本发明提供了能够处理具有一个或多个计算设备的集群的集群管理系统。 可能包含在群集中的计算设备的数量仅受实际考虑而不是软件或硬件限制的限制。 在一个实施例中，集群管理系统包括一组计算设备，其中一个计算设备是所有者。 集群还包括一个资源。 由计算设备直接访问资源由群集的所有者控制。 集群管理系统还包括仲裁器。 仲裁器和集群彼此通信，并且网络，群集为网络提供对存储设备的访问。 当集群的所有者不能接受新的计算设备时，仲裁器控制新的计算设备进入集群。 将仲裁者置于群集之外提供更高的可靠性。 仲裁器不受群集内的故障影响。 集群的一个或多个计算设备可能会失败，但集群的管理不受影响。 仲裁者的功能也可以分布在几个独立的计算设备之间，如果一个或多个独立计算设备不能令人满意地执行仲裁的责任，则可以将仲裁者的主要职责移交。
-
公开(公告)号：EP0869423A3
公开(公告)日：1999-11-24
申请号：EP98302457.1
申请日：1998-03-30
IPC分类号： G06F3/023
CPC分类号： G06F3/033 , G06F3/0489 , H04N5/4401 , H04N9/641 , H04N21/4143 , H04N21/4316 , H04N21/443 , H04N21/485 , H04N2005/4432
摘要： A method and apparatus allows users to quickly effect a modal change in an appliance, such as home theatre personal computer, having first and second modes. The apparatus captures a user actuation indicative of a modal change. The user actuation may be a mouse button closure, a keyboard button closure, or a remote control button closure. Upon detecting the user actuation indicative of a modal change, the apparatus detects the current mode for the appliance. Based on the current mode of the appliance, the apparatus cycles to the next mode in a round-robin basis and sets the next mode to become the current mode for the appliance. Further, in setting the next mode, the apparatus displays the next mode of the appliance as a mode change item in a menu list. The apparatus also then requests a second user actuation confirming a modal change. Further, in the event that the user confirms the modal change, the apparatus sets the next mode of the appliance to be the current mode for the appliance and maximizes the window associated with the mode of the appliance.
-
-
-
-
-
-
-
-
-
搜索结果
867 条记录 (耗时 0.015 秒)
