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公开(公告)号：EP1583242A1
公开(公告)日：2005-10-05
申请号：EP04425242.7
申请日：2004-04-01
IPC分类号： H03M1/00
摘要： The described analog-digital converter comprises quantization means (DAC, COMP) having an input for receiving an analog quantity to be converted (VIN), a register (REG) having an output (OUTBUS) for providing a digital quantity corresponding to the analog quantity, a timing pulse generator (CLK-GEN) and logic means (LOG) connected to the quantization means (DAC, COMP), the register (REG) and the timing pulse generator (CLK-GEN) and capable of responding to a conversion request signal (CONVREQ) by activating the quantization means in such a manner as to make them carry out predetermined operations timed by the timing pulses and load into the register (REG) the digital quantity to be provided at the output (OUTBUS).
With a view to permitting the converter to function even when a system clock is not available, the timing pulse generator (CLK-GEN), which is incorporated in the integrated circuit that comprises the rest of the converter, comprises an oscillator capable of being started/stopped by a binary signal applied to its activation input (STOP) and the logic means are capable of generating a stop signal (RESOSC) of the oscillator and comprise means (MONOST, OR) for generating the binary signal to be applied to the activation input (STOP) of the oscillator (CLK-GEN). This signal assumes a first or a second binary state corresponding, respectively, to activation and deactivation of the oscillator in response to, respectively, the conversion request signal (CONVREQ) and the stop signal (RESOSC) of the oscillator.摘要翻译： 所描述的模数转换器包括具有用于接收待转换的模拟量（VIN）的输入的量化装置（DAC，COMP），具有用于提供与模拟量对应的数字量的输出（OUTBUS）的寄存器（REG） ，连接到量化装置（DAC，COMP），寄存器（REG）和定时脉冲发生器（CLK-GEN）并能够响应转换请求的定时脉冲发生器（CLK-GEN）和逻辑装置 信号（CONVREQ）通过激活量化装置以使它们执行由定时脉冲定时的预定操作并将要在输出端（OUTBUS）提供的数字量加载到寄存器（REG）中来实现。 为了即使当系统时钟不可用时也允许转换器起作用，集成在包括转换器的其余部分的集成电路中的定时脉冲发生器（CLK-GEN）包括能够被启动的振荡器 /由施加到其激活输入（STOP）的二进制信号停止，并且该逻辑装置能够产生该振荡器的停止信号（RESOSC）并且包括用于产生将被应用于激活的二进制信号的装置（MONOST，OR） 振荡器的输入（STOP）（CLK-GEN）。 该信号呈现分别对应于振荡器响应于振荡器的转换请求信号（CONVREQ）和停止信号（RESOSC）的激活和去激活的第一或第二二进制状态。
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公开(公告)号：EP1564886A1
公开(公告)日：2005-08-17
申请号：EP04425083.5
申请日：2004-02-10
摘要： The described circuit comprises a first stage with an inverter (INV1), a capacitor (C1) connected to the input terminal of the inverter, a constant current generator (G1) and an electronic switch (M1) controlled by an input pulse (IN). The capacitor (C1) begins to charge at a predetermined edge of the input pulse and brings the input terminal of the inverter (INV1) from a first voltage (ground) to the switching threshold voltage of the inverter, so that on the output terminal of the inverter there is obtained a pulse having an edge that, as referred to the predetermined edge of the input pulse, has a delay time that depends on the inverter threshold. With a view to obtaining a delay time substantially independent of the inverter threshold, the circuit comprises a second stage, coupled with the first, that is a dual circuit of the circuit of the first stage and has an inverter (INV2) equal to the one of the first stage. The delay time of the circuit is given by the sum of the time needed to charge the capacitor (C1) of the first stage from ground to the threshold voltage and the time needed to discharge the capacitor (C2) of the second stage from the supply voltage (VDD) to the threshold voltage. This sum is independent of the threshold values of the inverters.
摘要翻译： 所描述的电路包括具有逆变器（INV1）的第一级，连接到逆变器的输入端的电容器（C1），恒定电流发生器（G1）和由输入脉冲（IN）控制的电子开关（M1） 。 电容器（C1）开始在输入脉冲的预定边缘充电，使逆变器（INV1）的输入端从第一电压（接地）转换到逆变器的开关阈值电压，使得在输出端 逆变器获得具有如参照输入脉冲的预定边缘具有取决于逆变器阈值的延迟时间的边缘的脉冲。 为了获得基本上与逆变器阈值相当的延迟时间，电路包括与第一级耦合的第二级，即第一级的电路的双电路，并且具有等于第一级的反相器（INV2） 的第一阶段 电路的延迟时间由第一级的接地电容器（C1）向阈值电压充电所需的时间和从供电电路的第二级电容器（C2）放电所需的时间之和给出 电压（VDD）达到阈值电压。 该和与反相器的阈值无关。
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33.发明授权Area-efficient reconstruction filters, particularly for D/A current-driven converters 失效表面有效重建滤波器，特别是用于电流控制的D / A转换器
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34.发明公开Area-efficient reconstruction filters, particularly for D/A current-driven converters 失效FlächeneffizientesRekonstruktionsfilter，insbesonderefürstromgesteuerte D / A-Wandler
公开(公告)号：EP0899873A1
公开(公告)日：1999-03-03
申请号：EP97830429.3
申请日：1997-08-29
CPC分类号： H03H11/126
摘要： An area-efficient low-pass, time-invariant, second-order reconstruction filter, particularly for current-driven digital-to-analog converters, comprising: a first resistor (R 1 ) and a first capacitor (C 1 ) which are parallel connected; an operational amplifier (3); a terminal of a second resistor (R 2 ) which is connected to the inverting input of the operational amplifier; another terminal of the second resistor which is connected to a common node of the first resistor (R 1 ) and the first capacitor (C 1 ); a second capacitor (C 2 ), which is fedback between the output of the operational amplifier and the inverting input; the filter further comprising an additional pair of resistors (R 3A , R 3B ) which are arranged so as to be fedback between the output and the inverting input, a current signal (I DAC ) arriving from a digital-to-analog converter arranged upstream of the reconstruction filter being fed to a common node of the additional pair of resistors.
摘要翻译： 一种区域有效的低通，时不变的二阶重构滤波器，特别是用于电流驱动的数模转换器，包括：并联连接的第一电阻器（R1）和第一电容器（C1） 运算放大器（3）; 连接到运算放大器的反相输入端的第二电阻器（R2）的端子; 连接到第一电阻器（R1）和第一电容器（C1）的公共节点的第二电阻器的另一个端子; 第二电容器（C2），其在运算放大器的输出端和反相输入端之间反馈; 所述滤波器还包括另外的一对电阻器（R3A，R3B），其被配置为在所述输出和所述反相输入端之间反馈，从布置在所述重建的上游的数模转换器到达的电流信号（IDAC） 滤波器被馈送到附加的一对电阻器的公共节点。
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