公开(公告)号：EP0170977A3

公开(公告)日：1988-03-16

申请号：EP85109248

申请日：1985-07-24

申请人： Honeywell Bull Inc.

发明人： Bruce, Kenneth E. ,  Holtey, Thomas ,  Goss, Gary J.

IPC分类号： G09G01/16

CPC分类号： G09G5/393

摘要： A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

公开(公告)号：EP0197499A3

公开(公告)日：1987-12-02

申请号：EP86104480

申请日：1986-04-02

申请人： Honeywell Bull Inc.

发明人： Hirsch, Thomas S. ,  Stonier, James W. ,  Holtey, Thomas O.

IPC分类号： G06F15/16 ,  G06F13/16

CPC分类号： G06F15/167 ,  G06F13/1663

摘要： 57 A computer system is described wherein two independent processors communicate via a bus system and operate substantially concurrently, each computer having its own operating system software and share a common memory. The architecture of the computer system is such that one of the processors is allocated the bulk of memory band-width with the other processor taking the remainder. Arbitration for memory allocation is accomplished via a combination of a new firmware instruction and a semaphore.

公开(公告)号：EP0177848A2

公开(公告)日：1986-04-16

申请号：EP85112234.1

申请日：1985-09-26

申请人： Honeywell Bull Inc.

发明人： Bradley, John J.

IPC分类号： G06F15/06 ,  G06F12/06

CPC分类号： G06F15/7842 ,  G06F1/22 ,  G06F12/0623

摘要： A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

公开(公告)号：EP0175341A2

公开(公告)日：1986-03-26

申请号：EP85111732.5

申请日：1985-09-17

申请人： Honeywell Bull Inc.

发明人： Bruce, Kenneth E.

IPC分类号： G09G1/16

CPC分类号： G09G5/14 ,  G09G5/40

摘要： The invention pertains to a computer display system for displaying text and graphics on a scan line basis wherein a scan line windowing apparatus for selectively blanking the graphics display is provided.
A bit map memory, in addition to storing information to be displayed on a CRT, further stores a bit for each scan line which is utilized to control the enabling or disabling of a portion of the information in the bit map memory which is to be displayed on the CRT.

公开(公告)号：EP0167806A1

公开(公告)日：1986-01-15

申请号：EP85106832.0

申请日：1985-06-03

申请人： Honeywell Bull Inc.

发明人： Rathbun, Donald J. ,  Tarbox, Bruce H. ,  Su, Taian

IPC分类号： G11B5/09

CPC分类号： G11B20/1883 ,  G11B2020/10916 ,  G11B2220/20

摘要： A disk drive of a mass storage subsystem includes areas on a disk surface wherein a vendor-generated defective sector log, a software-generated defective sector log and an alternate sector log are stored. A random access memory (RAM) stores a copy of the defective sector logs. During a seek operation, firmware tests the defective sector logs in RAM to generate the alternate sector log for that cylinder number. During the read or write operation, the alternate sector log is checked before processing the sector to determine if it is a defective sector. If the sector is defective, the head is positioned to another cylinder at a head and sector address read from the alternate sector log.

公开(公告)号：EP0162454A2

公开(公告)日：1985-11-27

申请号：EP85106272.9

申请日：1985-05-22

申请人： Honeywell Bull Inc.

发明人： Tarbox, Bruce H. ,  Rathbun, Donald J. ,  Su, Taian

IPC分类号： G06F3/06 ,  G11B20/12

CPC分类号： G06F3/0607 ,  G06F3/064 ,  G06F3/0676 ,  G11B20/1252 ,  G11B2220/2508

摘要： A track of a disk device is formatted on a single revolution of the disk by using a read only memory (ROM) to store control codes and a random access memory (RAM) to store address field and data field bytes. A DMA controller simultaneously addresses ROM and RAM. Control codes are read into a control first in-first out memory and data codes are read into a data first in-first out memory. The control codes are applied to a decoder whose output signals control cyclic redundancy check and error detection and correction logic as well as the data first in-first out memory. The serial output from both the data first in-first out memory and the cyclic redundancy check logic are written on disk track.

公开(公告)号：EP0140158A2

公开(公告)日：1985-05-08

申请号：EP84111464.8

申请日：1984-09-26

申请人： Honeywell Bull Inc.

发明人： Bradley, John J. ,  Stoffers, Brian L. ,  Widen, Melinda A.

IPC分类号： G06F5/00 ,  H03M7/08

CPC分类号： H03M7/08

摘要： A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is described. The CPU includes a microprocessor which executes the binary arithmetic software instructions under firmware control. The CPU also includes commercial instruction logic which is used in conjunction with the microprocessor to execute decimal arithmetic operations. The commercial instruction logic also operates under firmware control with the addressing of the firmware microinstructions being controlled by the microprocessor. Also disclosed is the method by which the CPU performs decimal addition, subtraction, multiplication and division arithmetic operations and the method used to convert a number in a binary format to a number in a decimal format and the method used to convert a number in a decimal format to a number in a binary format.

公开(公告)号：EP0088838A1

公开(公告)日：1983-09-21

申请号：EP82301275.2

申请日：1982-03-12

申请人： Honeywell Bull Inc.

发明人： Crawford, Knute S.

IPC分类号： G06F13/00

CPC分类号： G06F13/122

摘要： An input/output multiplexer 20 couples a central subsystem 3 to peripheral subsystems 4 containing several units. Information flows from the central subsystem to the peripheral subsystems through a central subsystem data distributor 21, a switch 25, and a peripheral subsystems access controller 26; and in the reverse direction through a peripheral subsystems data controller 27, a channel service processor 28, a switch 29, and a central subsystem access controller 20. Information relating to different subsystems can be at different stages in its passage simultaneously. A control word processor 24 and scratch pad memory 31 stores files from the central subsystem and prepares real addresses, and the channel service processor 28 obtains these addresses, in response to signals from the peripheral subsystems, and incorporates them in the information flowing to the central subsystem.

摘要翻译： 输入/输出多路复用器20将中央子系统3耦合到包含若干单元的外围子系统4。 信息通过中央子系统数据分配器21，开关25和外围子系统访问控制器26从中央子系统流向外围子系统; 并且通过外围子系统数据控制器27，信道服务处理器28，交换机29和中央子系统访问控制器20在相反方向上。与不同子系统相关的信息可以在其同时通过的不同阶段。 控制字处理器24和便签存储器31存储来自中央子系统的文件并准备实际地址，并且信道服务处理器28响应于来自外围子系统的信号而获得这些地址，并且将它们并入到流向中央的信息 子系统。

公开(公告)号：EP0087266A2

公开(公告)日：1983-08-31

申请号：EP83300778.4

申请日：1983-02-16

申请人： Honeywell Bull Inc.

发明人： Brown, Richard P. ,  Lemay, Richard A. ,  Steiner, Lewis G. ,  Woods, William E.

IPC分类号： G06F13/00

CPC分类号： G06F13/18

摘要： A priority resolution circuit has four flip-flops CPF, SIF, CIF, and FIF for the four possible requesting units. Setting a low priority flip-flop, e.g. CPF, prevents later setting of a higher priority one by gates 33 to 35, but a high priority one can be set substantially simultaneously with a low priority one. Output gates CPG, SIG, CIG, select the highest priority flip-flop which is set. The setting of any flip-flop fires a timing circuit by pulse TCF, and this enables the gates CPG, SIG, CIG by pulse CLR after all possible transients have decayed. The timing circuit may have its timing controlled by the selected unit (CPU, SIP, CIP, or MBA) via a selector controlled by the flip-flops CPF, SIF, CIF, and FIF.

摘要翻译： 优先级分辨率电路具有四个触发器CPF，SIF，CIF和FIF，用于四个可能的请求单元。 设置低优先级触发器，例如 CPF防止稍后通过门33至35设置较高优先级，但是可以与低优先级基本上同时设置高优先权。 输出门CPG，SIG，CIG，选择设置的最高优先级触发器。 任何触发器的设置通过脉冲TCF触发定时电路，并且这在所有可能的瞬变衰减之后通过脉冲CLR使门CPG，SIG，CIG成为可能。 定时电路可以通过由触发器CPF，SIF，CIF和FIF控制的选择器由所选择的单元（CPU，SIP，CIP或MBA）控制其定时。

公开(公告)号：EP0072179A2

公开(公告)日：1983-02-16

申请号：EP82304086.0

申请日：1982-08-03

申请人： Honeywell Bull Inc.

发明人： Webster, Marvin K. ,  Flynn, Richard T. ,  Porter, Marion G. ,  Seminsky, George M.

IPC分类号： G06F12/08

CPC分类号： G06F12/0808

摘要： A cache memory comprises a directory 202 and a data store 201. The n-bit portion of a desired address from an associated CPU selects a location in directory 202, and the m-bit address portions in the 4 levels I to IV of that location are compared at 203 with the m-bit portion of the desired address. On a match, the corresponding level of the corresponding location of the data store 201 is accessed to access the desired word.
The cache words should mirror the contents of the main memory, but the latter may be changed by e.g. another CPU or an IOC, and the resulting invalid addresses must be cleared from the cache memory. This is done by searching the directory 202 for an invalid address during the second half of a cache cycle, after the directory has been searched to determine whether the desired word is in the cache and while that desired word is being accessed in the cache store 201. If an invalid address is found, the second half of the next cache cycle is used to clear it from the cache, by resetting the full/empty indicator in the directory control portion C for that level and that location.

摘要翻译： 高速缓冲存储器包括目录202和数据存储201.来自相关CPU的期望地址的n位部分选择目录202中的位置，并且该位置的4级I至IV中的m位地址部分 在203与所需地址的m位部分进行比较。 在匹配时，访问数据存储201的对应位置的相应级别以访问所需的字。 ... 缓存字应该镜像主存储器的内容，但后者可以通过例如 另一个CPU或IOC，并且所得到的无效地址必须从缓存中清除。 这是通过在高速缓存周期的后半部分中搜索目录202的无效地址之后，在目录被搜索以确定期望的字是否在高速缓存中并且在该高速缓存存储器201中正在访问该期望的字的情况下 如果发现无效地址，则通过重置目录控制部分C中该级别和该位置的完整/空指示符，将下一个高速缓存周期的后半部分从高速缓存中清除。