公开(公告)号：EP3152670A1

公开(公告)日：2017-04-12

申请号：EP15731175.4

申请日：2015-06-05

申请人： Microchip Technology Incorporated

发明人： KRIS, Bryan

IPC分类号： G06F15/76 ,  G06F1/22

CPC分类号： G06F13/385 ,  G06F1/22 ,  G06F13/287 ,  G06F15/76

摘要： An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

摘要翻译： 嵌入式设备具有多个处理器核心，每个处理器核心具有多个外围设备，其中每个外围设备可以具有输出，具有多个可分配外部引脚的外壳以及用于每个处理核心的多个外围引脚选择模块， 其中每个外围引脚选择模块被配置为可编程以将可分配的外部引脚分配给所述处理器核心之一的所述多个外围设备之一。

公开(公告)号：EP1605334A3

公开(公告)日：2012-02-15

申请号：EP05102655.7

申请日：2005-04-04

申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

发明人： Merk, Dieter

IPC分类号： G06F1/22

CPC分类号： G01R31/31701 ,  G01R31/3172 ,  G06F1/22

摘要： An interface circuit for a single logic input pin of an electronic system, comprising a decoder 10 for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine 12 responsive to said sequence of logic values to switch the electronic system between different modes of operation.

公开(公告)号：EP1130501B1

公开(公告)日：2009-07-15

申请号：EP01000035.4

申请日：2001-03-02

申请人： Texas Instruments Incorporated

发明人： Swoboda, Gary L. ,  Deao, Douglas E.

IPC分类号： G06F1/22 ,  G01R31/3185 ,  G06F11/34

CPC分类号： G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

摘要： An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

公开(公告)号：EP1964267A1

公开(公告)日：2008-09-03

申请号：EP06818605.5

申请日：2006-11-16

申请人： Austriamicrosystems AG

发明人： GREIMEL-RECHLING, Bernhard ,  TRATTLER, Peter

IPC分类号： H03K19/173 ,  G06F1/22

CPC分类号： G06F1/22 ,  H03K19/1732

摘要： An input circuit arrangement (1) has an input (2), a comparator (30) and an evaluation circuit (50). The input (2) is designed for being coupled to a first connection (101) of an impedance (100) and for supplying an input signal (ES). The comparator (30) is connected to the input (2) of the input circuit arrangement (1) and is designed to output an activation signal (S1) at an output (31) as a function of a comparison of the input signal (ES) with a threshold value (SW1) which can be set. Furthermore, the evaluation circuit (50) is connected to the input (2) of the input circuit arrangement (1) and, in order to activate it, to the output (31) of the comparator (30) and is designed to evaluate the value of the impedance (100) which can be connected.

公开(公告)号：EP1828868A2

公开(公告)日：2007-09-05

申请号：EP05851883.8

申请日：2005-11-16

申请人： Cirrus Logic, Inc.

发明人： NANDA, Kartik

IPC分类号： G06F1/22

CPC分类号： G06F1/22 ,  H03M3/396 ,  H03M3/50

摘要： Mode selection circuitry selects one a plurality of plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.

公开(公告)号：EP1634402A2

公开(公告)日：2006-03-15

申请号：EP04754398.8

申请日：2004-06-04

申请人： Cirrus Logic, Inc.

发明人： DUEWER, Bruce, Eliot

IPC分类号： H04L1/00

CPC分类号： G11B20/10527 ,  G06F1/22 ,  G11B2020/00065 ,  G11B2020/10583

摘要： A method of controlling a terminal of an integrated circuit includes determining a frequency ratio between a frequency of a signal and a frequency of another signal received by an integrated circuit. A selected signal appearing at a selected terminal of the integrated circuit is selectively interpreted in accordance with an operating mode when the frequency ratio is below a selected value and in accordance with another operating mode when the frequency of the signal is above a selected value.

公开(公告)号：EP1132816A3

公开(公告)日：2005-09-07

申请号：EP01200793.6

申请日：2001-03-02

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Swoboda, Gary L.

IPC分类号： G06F11/26 ,  G06F11/267

CPC分类号： G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

摘要： Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chipl, ChipN) and the emulation controller (12) tri-state respective terminals thereof, one of the target devices drives a predetermined logic level on each of the aforementioned terminals thereof in sequence, while maintaining the remainder of the aforementioned terminals thereof tri-stated. These driving (33) and maintaining (31) operations are thereafter performed by each of the remaining target devices in sequence. During each driving step, all of the target devices and the emulation controller read logic levels at their aforementioned terminals (34, 43).

公开(公告)号：EP0639006B1

公开(公告)日：2003-10-22

申请号：EP94202212.0

申请日：1994-07-28

申请人： LATTICE SEMICONDUCTOR CORPORATION

发明人： Tsui, Cyrus Y ,  Chan, Albert L ,  Shankar, Kapil ,  Shen, Ju

IPC分类号： H03K19/173

CPC分类号： G06F17/5054 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G06F1/22 ,  H03K19/1732 ,  H03K19/1737

公开(公告)号：EP1139108A2

公开(公告)日：2001-10-04

申请号：EP01200790.2

申请日：2001-03-02

申请人： Texas Instruments Incorporated

发明人： Swoboda, Gary L.

IPC分类号： G01R31/3185

CPC分类号： G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

摘要： A scan interface that includes control signals (TRST, TMS, TCK) and data signals (TDI, TDO) normally carried by respective signal paths of the scan interface can be used to carry signals other than signals of the scan interface. A first signal (TMS) and a second signal (TDO) can be time division multiplexed on the signal path that normally carries one of the signals, thereby freeing the signal path that carries the other of the signals to carry a signal other than a signal of the scan interface.

摘要翻译： 包括通常由扫描接口的各个信号路径携带的控制信号（TRST，TMS，TCK）和数据信号（TDI，TDO）的扫描接口可用于承载扫描接口信号以外的信号。 第一信号（TMS）和第二信号（TDO）可以在通常携带信号之一的信号路径上进行时分复用，从而释放携带另一个信号的信号路径以承载除信号之外的信号 的扫描界面。

公开(公告)号：EP1132816A2

公开(公告)日：2001-09-12

申请号：EP01200793.6

申请日：2001-03-02

申请人： Texas Instruments Incorporated

发明人： Swoboda, Gary L.

IPC分类号： G06F11/26

CPC分类号： G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

摘要： Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chipl, ChipN) and the emulation controller (12) tri-state respective terminals thereof, one of the target devices drives a predetermined logic level on each of the aforementioned terminals thereof in sequence, while maintaining the remainder of the aforementioned terminals thereof tri-stated. These driving (33) and maintaining (31) operations are thereafter performed by each of the remaining target devices in sequence. During each driving step, all of the target devices and the emulation controller read logic levels at their aforementioned terminals (34, 43).

摘要翻译： 可自动检测在仿真控制器和目标设备的之间的多个连接。 目标设备（芯片1，ChipN）和仿真控制器后体（12）的三态respectivement终端，所述目标装置中的一个驱动每个上述端子在序列或其的预定逻辑电平，同时保持上述的其余部分 它们的端子三态。 这些驱动（33）和维护（31）的操作是由每个序列中剩余的目标设备的此后进行。 在每个驱动步骤中，所有的目标设备和仿真控制器读取的逻辑电平在其前述端子（34，43）的。