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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
    32.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM 审中-公开

    公开(公告)号：EP3620929A1

    公开(公告)日：2020-03-11

    申请号：EP19204049.1

    申请日：2016-07-20

    申请人： Toshiba Memory Corporation

    发明人： Tokiwa, Naoya

    IPC分类号： G06F12/02 ,  G06F13/16 ,  G11C7/10 ,  G06F3/06 ,  G11C16/32

    摘要： A memory system includes a semiconductor memory device including a plurality of memory cells, and a memory controller. The semiconductor memory device includes first, second, and third caches for storing data before the data are written into the memory cells. The memory controller is configured to issue commands to the semiconductor memory device, the commands including a first command issued with write data to store the write data in the first cache and a second command issued with write data to store the write data in the first cache and then transfer the write data in the first cache to one of the second and third caches.

    SEMICONDUCTOR STORAGE DEVICE
    34.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：EP3598493A1

    公开(公告)日：2020-01-22

    申请号：EP18768470.9

    申请日：2018-01-19

    申请人： Toshiba Memory Corporation

    发明人： KOYANAGI, Masaru

    IPC分类号： H01L27/10 ,  G11C5/04 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

    摘要： A semiconductor memory device includes a first and second substrates; and a first and second element layers respectively provided on an upper surface of the first and the second substrates. The first and second substrates respectively include a first and second vias. The first and second element layers respectively includes a first and second pads respectively electrically coupled to the first and second vias, and respectively provided on an upper surface of the first and second element layers. The upper surface of the second element layer is arranged so as to be opposed to the upper surface of the first element layer. The first and second pads are electrically coupled and symmetrically arranged with respect to a surface where the first and second element layers are opposed to each other.

    MEMORY DEVICE AND HOST DEVICE
    37.
    发明公开
    MEMORY DEVICE AND HOST DEVICE 审中-公开

    公开(公告)号：EP3518112A1

    公开(公告)日：2019-07-31

    申请号：EP19160700.1

    申请日：2013-09-10

    申请人： TOSHIBA MEMORY CORPORATION

    发明人： Fujimoto, Akihisa

    IPC分类号： G06F12/02

    摘要： According to one embodiment, a memory device includes a nonvolatile semiconductor memory, a management unit, and a control unit. The nonvolatile semiconductor memory has a plurality of physical storage areas that includes a user area externally accessible and are divided into plurality of management units. The control unit is configured to control the nonvolatile semiconductor memory. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

    ON THE FLY RAID PARITY CALCULATION
    38.
    发明公开
    ON THE FLY RAID PARITY CALCULATION 审中-公开

    公开(公告)号：EP3495955A2

    公开(公告)日：2019-06-12

    申请号：EP18189925.3

    申请日：2018-08-21

    申请人： Toshiba Memory Corporation

    发明人： Margetts, Julien

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1068 ,  G06F11/1076 ,  G11C29/52

    摘要： A data storage device comprises a nonvolatile semiconductor storage array containing data, a controller in communication with the nonvolatile semiconductor storage array, and a buffer containing RAID units, the RAID units being in communication with the nonvolatile semiconductor storage array via the controller. The controller is configured to receive write requests from a host device, and accumulate first data relating to the write requests in the RAID units. The controller is also configured to, concurrently, transfer the first data contained in the RAID units to the nonvolatile semiconductor storage array, calculate parity values of the first data contained in the RAID units, each parity value relating to each write request, and accumulate the parity values in a context identifier buffer. The controller is further configured to associate context identifiers with the parity values, and store the parity values and the context identifiers in the nonvolatile semiconductor storage array.