公开(公告)号：EP0642095A3

公开(公告)日：1996-07-31

申请号：EP94306540.9

申请日：1994-09-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  PHILIPS ELECTRONICS N.V.

发明人： Hughes, John Barry, c/o Philips Res.Lab. ,  Moulding, Kenneth William, c/o Philips Res.Lab.

IPC分类号： G06G7/186

CPC分类号： G06G7/1865

摘要： A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which during a first phase of a clock cycle an input current is fed to the inputs of the current memory cells and during a second phase of a clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2) . A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell (N2) and an inverted, scaled version of the current stored in the first memoy cell (M1).

公开(公告)号：EP0571075A2

公开(公告)日：1993-11-24

申请号：EP93302544.7

申请日：1993-03-31

申请人： HEWLETT-PACKARD COMPANY

发明人： Baumgartner, Richard A. ,  Moore, Charles E. ,  Herleikson, Earl C.

IPC分类号： H03M1/18 ,  H03F3/00 ,  G06G7/18

CPC分类号： H03M1/005 ,  A61B5/0428 ,  A61B5/7203 ,  A61B5/7242 ,  G06G7/1865 ,  H03F3/005 ,  H03F3/393 ,  H03F2200/261 ,  H03F2200/331 ,  H03M1/181 ,  H03M1/504 ,  H03M3/392 ,  H03M3/398 ,  H03M3/48 ,  H03M3/488

摘要： In a mixed analog and digital integrated circuit for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs, an AD converter (346) adds an analog signal input (416) to an analog offset input to produce a digital signal output (724), and an offset means (736,740) generates the analog offset input if the digital output exceeds a threshold (1006,1008) for a predetermined number of A/D conversion. The integrated circuit has five signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has two digital serial input lines and two digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to six compatible devices can be serially connected in a chain.

摘要翻译： 在用于诸如心电图仪，肌电图和脑电图仪的生理信号仪器的混合模拟和数字集成电路中，AD转换器（346）将模拟信号输入（416）添加到模拟偏移输入以产生数字信号输出（724）， 如果数字输出超过预定数量的A / D转换的阈值（1006,1008），则偏移装置（736,740）产生模拟偏移输入。 该集成电路有五个信号通道，每个通道具有模拟放大和模数转换。 通道可配置为输入信号放大，输入信号求和，模拟输出驱动和交流阻抗测量的各种组合。 集成电路具有两条数字串行输入线和两条数字串行输出线，全部设计用于直接连接光耦合器。 通道配置，增益和其他参数可通过串行数字输入信号进行外部控制。 多达六个兼容的设备可以串连在一起。

公开(公告)号：EP0030824B1

公开(公告)日：1987-06-24

申请号：EP80304374.4

申请日：1980-12-04

申请人： FUJITSU LIMITED

发明人： Akihiko, Ito ,  Kazuhiro, Kobayashi ,  Hisami, Tanaka ,  Norio, Ueno

IPC分类号： G06G7/186 ,  H03H19/00

CPC分类号： H03H19/004 ,  G06G7/1865

公开(公告)号：EP0114314A2

公开(公告)日：1984-08-01

申请号：EP83112677.6

申请日：1983-12-16

申请人： INTERSIL, INC.

发明人： Bingham, David ,  Evans, Lee Leland ,  Bradshaw, Peter Duncan

IPC分类号： G06G7/12

CPC分类号： H03F3/45977 ,  G06G7/14 ,  G06G7/161 ,  G06G7/1865 ,  H03F2200/261 ,  H03F2203/45551

摘要： A digitally switched analog signal conditioner comprising a plurality of pairs of input terminals, a junction, and an output terminal; a plurality of capacitors, first ends of the capacitors being connected to the junction; a plurality of switches being arranged in pairs, first ends of each pair being connected to the other ends of different ones of the capacitors, the other ends of each pair being connected to respective ones of a pair of input terminals, the switches of each pair being adapted to be operated alternatively; an amplifier having an input and an output, the input being operatively coupled to the junction; and a sample and hold circuit operatively coupled to the output of the amplifier for periodically sampling and holding the output, the output of the sampling and holding circuit being connected to one of the input terminals of one of the pairs of input terminals, the other of the terminals of the one pair of input terminals being connected to a point of reference potential.

公开(公告)号：EP0025377B1

公开(公告)日：1983-04-20

申请号：EP80401186.4

申请日：1980-08-13

申请人： THOMSON-CSF

发明人： Ricodeau, Jean ,  Roziere, Guy

IPC分类号： G06G7/184 ,  G11C27/02

CPC分类号： G11C27/026 ,  G06G7/1865

公开(公告)号：EP0071528A2

公开(公告)日：1983-02-09

申请号：EP82401372.6

申请日：1982-07-23

申请人： AMERICAN MICROSYSTEMS, INCORPORATED

发明人： Gregorian, Roubik ,  Wegner, Glenn

IPC分类号： G06G7/186

CPC分类号： G06G7/1865

摘要： An integrator circuit utilizing an operational amplifier (19) and switched capacitor elements (11.13 and 16) in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage (V OUT ) free from the effects of voltage offsets inherent in operational amplifiers.

公开(公告)号：EP0030824A1

公开(公告)日：1981-06-24

申请号：EP80304374.4

申请日：1980-12-04

申请人： FUJITSU LIMITED

发明人： Akihiko, Ito ,  Kazuhiro, Kobayashi ,  Hisami, Tanaka ,  Norio, Ueno

IPC分类号： G06G7/186 ,  H03H19/00

CPC分类号： H03H19/004 ,  G06G7/1865

摘要： The switched capacitor comprises a capacitor CA 1 and a switching element S which can be periodically changed over for charging CA, with an input voltage V IN and for discharging the capacitor CA, to one input end (A) of an operational amplifier OP,. Another input end of OP, is connected to a reference potential (ground) and an integrating capacitor CB, is connected between an output end of OP, and the input end (A).
Switching elements S 2 and S 3 are connected to input end (A) and the output end of OP 1 . The switching elements can be closed to make the potentials of the input end (A) and the output end of OP 1 equal to the reference potential (ground).
This prevents potentials at input end (A) and the output end becoming unfixed when the integrator is out of operation, and ensures rapid stabilization of operation when the integrator is brought into operation.

摘要翻译： 开关电容器包括电容器CA1和开关元件S1，开关元件S1可以周期性地改变以便用输入电压YIN对CA1充电，并且将电容器CA1放电到运算放大器OP1的一个输入端（A）。 0P1的另一个输入端连接到参考电位（地），并且积分电容器CB1连接在OP1的输出端和输入端（A）之间。开关元件S2和S3连接到输入端 A）和OP1的输出端。 开关元件可以闭合，使输入端（A）的电位和OP1的输出端等于参考电位（地）。 ... 这样可以防止输入端（A）的电位和输出端在积分器停止运行时变得不固定，并确保在积分器运行时快速稳定运行。

公开(公告)号：EP0025377A1

公开(公告)日：1981-03-18

申请号：EP80401186.4

申请日：1980-08-13

申请人： THOMSON-CSF

发明人： Ricodeau, Jean ,  Roziere, Guy

IPC分类号： G06G7/184 ,  G11C27/02

CPC分类号： G11C27/026 ,  G06G7/1865

摘要： Dispositif de commutation d'un condensateur de stockage qui est constitué par trois circuits montés en parallèle qui comportent une porte analogique de commutation (Z 1 ,Z 2 , Z 3 ) en série avec une résistance (R 1 ,R 2 , R 3 ). Ce dispositif est monté en parallèle sur un condensateur (C) dont il assure la décharge en trois étapes. A chaque étape, une seule porte est ouverte selon l'ordre croissant des résistances (R 1 , R 2 , R 3 ).

摘要翻译： 1.设备用于切换存储电容器，确保充电或安装在串联或平行于该设备的存储电容器的放电，分别，其特征在于它也包括并联连接的N个电路和由形成的栅极串联模拟与电阻器 ，并在DASS模储存电容器通过n步，通过该保证的等效电阻的在所述设备从一个步骤到以下的增加而模拟门的开关切换。

公开(公告)号：EP3183821A1

公开(公告)日：2017-06-28

申请号：EP15763120.1

申请日：2015-08-15

申请人： Qualcomm Incorporated

发明人： ALLADI, Dinesh Jagannath ,  GUO, Yuhua

IPC分类号： H03M3/02 ,  G06G7/186 ,  H03M3/04

CPC分类号： G06G7/186 ,  G06G7/1865 ,  H03M3/32 ,  H03M3/342 ,  H03M3/344 ,  H03M3/496 ,  H03M3/50

摘要： Certain aspects of the present disclosure provide various sampling networks for switched-capacitor integrators, which may be used in switched-capacitor analog-to-digital converters (ADCs). Rather than having both an input sampling capacitor and a reference sampling capacitor, certain aspects of the present disclosure use a shared sampling capacitor for the reference voltage and the input voltage, thereby reducing ADC input-referred noise, decreasing op amp area and power, and avoiding anti-aliasing filter insertion loss. Furthermore, by sampling the reference voltage during the sampling phase and sampling the input voltage during the integration phase using the shared sampling capacitor, a high-bandwidth reference buffer need not be used for the reference voltage.

摘要翻译： 本公开的某些方面提供用于开关电容积分器的各种采样网络，其可用于开关电容模数转换器（ADC）中。 本发明的某些方面不是同时具有输入采样电容器和参考采样电容器，而是使用用于参考电压和输入电压的共享采样电容器，从而降低ADC输入参考噪声，降低运算放大器面积和功率，以及 避免了抗混叠滤波器的插入损耗。 此外，通过在采样阶段采样参考电压并在采用共享采样电容的积分阶段对输入电压进行采样，不需要使用高带宽参考缓冲器作为参考电压。

公开(公告)号：EP1136798A4

公开(公告)日：2004-05-26

申请号：EP99973121

申请日：1999-12-02

申请人： HAMAMATSU PHOTONICS KK

发明人： MIZUNO SEIICHIRO

IPC分类号： H04N5/32 ,  G01J1/44 ,  G06G7/186 ,  H01L31/10 ,  H03F3/30 ,  H03F3/45 ,  G01T1/20

CPC分类号： G06G7/1865 ,  G01J1/44 ,  H03F3/3001 ,  H03F3/45076

摘要： An integrator circuit (10) receiving a current signal from the anode terminal of a photodiode (PD) includes a two-input, two-output full-differential amplifier (A0), capacitors (C01, C02), switches (S01, S02, S11, S12), and an additional capacitor (Ca). The capacitor (C01) and the switch (S01) are connected in parallel between the negative and positive input terminals of the full-differential amplifier (A0). The negative input terminal of the full-differential amplifier (A0) is connected with the anode terminal of the photodiode (PD). The capacitor (C02) and the switch (S02) are connected in parallel between the positive and negative input terminals of the full-differential amplifier (A0). The positive input terminal of the full-differential amplifier (A0) is connected with the additional capacitor (Ca) whose capacitance is substantially equal to the junction capacitance of the photodiode (PD).

摘要翻译： 接收来自光电二极管（PD）的阳极端子的电流信号的积分器电路（10）包括双输入二输出全差分放大器（A0），电容器（C01，C02），开关（S01，S02， S11，S12）和附加电容器（Ca）。 电容器（C01）和开关（S01）并联在全差分放大器（A0）的负输入端和正输入端之间。 全差分放大器（A0）的负输入端与光电二极管（PD）的阳极端连接。 电容器（C02）和开关（S02）并联在全差分放大器（A0）的正和负输入端之间。 全差分放大器（A0）的正输入端与附加电容器（Ca）连接，该电容器的电容基本上等于光电二极管（PD）的结电容。