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52 条记录 (耗时 0.008 秒)

    Switched-current integrator
    3.
    发明公开
    Switched-current integrator 失效
    Stromschaltender积分器。

    公开(公告)号：EP0642095A2

    公开(公告)日：1995-03-08

    申请号：EP94306540.9

    申请日：1994-09-06

    申请人： PHILIPS ELECTRONICS UK LIMITED ,  PHILIPS ELECTRONICS N.V.

    发明人： Hughes, John Barry, c/o Philips Res.Lab. ,  Moulding, Kenneth William, c/o Philips Res.Lab.

    IPC分类号： G06G7/186

    CPC分类号： G06G7/1865

    摘要： A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which during a first phase of a clock cycle an input current is fed to the inputs of the current memory cells and during a second phase of a clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2) .
    A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell (N2) and an inverted, scaled version of the current stored in the first memoy cell (M1).

    摘要翻译： 一种开关电流双线性积分器，包括互连的当前存储单元（M1，M2），其中在时钟周期的第一阶段期间，将输入电流馈送到当前存储器单元的输入端，并且在时钟周期的第二阶段期间， （A1）输入到当前存储单元的输入端。 通过将第一当前存储器单元（M1）的输出（可选地缩放）与第二存储器单元（M2）的输出（可选地缩放）的反相（A2）版本组合来获得积分器的输出。 可以通过将存储在第二当前存储器单元（N2）中的电流的缩放版本和存储在第一备忘单元（M1）中的电流的反转的缩放版本反馈给输入来形成有损积分器。

    Ladungsverstärkerschaltung
    4.
    发明公开
    Ladungsverstärkerschaltung 失效
    充电放大器电路。

    公开(公告)号：EP0253016A1

    公开(公告)日：1988-01-20

    申请号：EP86109912.5

    申请日：1986-07-18

    申请人： Kistler Instrumente AG

    发明人： Büsser, Bruno ,  Amstutz, Leo

    IPC分类号： H03F3/70 ,  H03F1/30 ,  G06G7/186

    CPC分类号： H03F3/70 ,  G06G7/1865 ,  H03F1/303

    摘要： Die Ladungsverstärkerschaltung weist einen Operationsverstärker (V1) mit einem Integrationskondensator (C) zwischen seinem inver­tierenden Eingang und seinem Ausgang auf sowie eine Rückstellein­richtung mit einem in der Rückstellphase geschlossenen Schalter (S) für die Entladung des Integrationskondensators (C). Am Ausgang (A) der Ladungsverstärkerschaltung ist eine Schaltungsanordnung mit einem Korrekturverstärker (V3) vorgesehen, die bei geschlossenem Schalter (S) dem Integrationskondensator (C) automatisch eine Korrekturladung zuführt, welche während der Messphase die Null­punktablage der Ausgangsspannung der Ladungsverstärkerschaltung kompensiert. Diese Schaltungsanordnung eignet sich besonders für Ladungsverstärker mit extrem hochohmiger Eingangsstufe.

    摘要翻译： 电荷放大器电路具有运算放大器（V1）与它的反相输入端和其输出端，并具有在重置阶段开关（S）的积分电容器（C）的放电的封闭的复位装置之间的积分电容器（C）。 在电荷放大器电路的输出（A），一个电路装置由一个校正放大器（V3），其与一个闭合的开关（S）的积分电容器（C），其补偿在测量阶段的电荷放大器电路的输出电压的零点偏移的校正电荷自动进纸提供。 该电路特别适用于电荷放大器具有极高阻抗输入级。

    PHOTODETECTOR DEVICE
    8.
    发明授权
    PHOTODETECTOR DEVICE 无效
    光电检测设备

    公开(公告)号：EP1136798B1

    公开(公告)日：2009-03-11

    申请号：EP99973121.9

    申请日：1999-12-02

    申请人： HAMAMATSU PHOTONICS K.K.

    发明人： MIZUNO, Seiichiro

    IPC分类号： G01J1/44 ,  H01L31/10 ,  G01T1/20

    CPC分类号： G06G7/1865 ,  G01J1/44 ,  H03F3/3001 ,  H03F3/45076

    摘要： An integrator circuit (10) receiving a current signal from the anode terminal of a photodiode (PD) includes a two-input, two-output full-differential amplifier (A0), capacitors (C01, C02), switches (S01, S02, S11, S12), and an additional capacitor (Ca). The capacitor (C01) and the switch (S01) are connected in parallel between the negative and positive input terminals of the full-differential amplifier (A0). The negative input terminal of the full-differential amplifier (A0) is connected with the anode terminal of the photodiode (PD). The capacitor (C02) and the switch (S02) are connected in parallel between the positive and negative input terminals of the full-differential amplifier (A0). The positive input terminal of the full-differential amplifier (A0) is connected with the additional capacitor (Ca) whose capacitance is substantially equal to the junction capacitance of the photodiode (PD).

    Bipolar junction transistor charge transfer network
    9.
    发明公开
    Bipolar junction transistor charge transfer network 审中-公开
    与双极结型晶体管的电荷转移网络

    公开(公告)号：EP1246199A3

    公开(公告)日：2003-05-14

    申请号：EP02003497.1

    申请日：2002-02-15

    申请人： Siemens Information and Communication Networks S.p.A.

    发明人： Gatti, Umberto ,  Malcovati, Piero ,  Maloberti, Franco

    IPC分类号： G11C27/02 ,  H03M3/02

    CPC分类号： G11C27/024 ,  G06G7/1865 ,  H03M3/458

    摘要： Charge transfer network from a sampling capacitor (C 1 ) to an integration capacitor (C 2 ) consisting of two identical structures, made of a first branch and a second branch connected in parallel between a first node and a second node, respectively connected to the supply nodes through bias current generators, each branch consisting of a couple of switches in series, the sampling capacitor (C 1 ) being connected to a current common node (A) of the switches of the first branch of both the structures and the integration capacitor (C 2 ) being connected to the first node of the first structure, being the current common nodes (B) of the switches of the second branch of both the structures connected between them, the control signals of the switched of the first and second branches being cross-coupled to two control phases (Φ 1 , Φ 2 ). The charge transfer network is used in the implementation of switched-capacitors integrators of sigma-delta converters (Fig. 6a).

    Replica network for linearizig switched capacitor circuits
    10.
    发明公开
    Replica network for linearizig switched capacitor circuits 有权
    Replikatornetzwerk用于线性化开关电容器电路

    公开(公告)号：EP1227589A2

    公开(公告)日：2002-07-31

    申请号：EP02250157.1

    申请日：2002-01-10

    申请人： Broadcom Corporation

    发明人： Gupta, Sandeep K.

    IPC分类号： H03K17/14 ,  H03H19/00

    CPC分类号： G06G7/1865 ,  G11C27/026 ,  H03H19/004 ,  H03K17/063 ,  H03K17/145

    摘要： The present invention relates to a replica network (400) for linearizing switched capacitor circuits. A bridge circuit (406) with a MOSFET resistor (424) disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier (408) is connected to a first node (B) of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second note (D) of the bridge circuit. The second node is separated from the first node by another node (C) of the bridge circuit. An output of the operational amplifier (408) is provided to a gate terminal of the MOSFET resistor (424) and to the gate terminal of the MOSFET switch (204) in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.