公开(公告)号：EP0157779A1

公开(公告)日：1985-10-16

申请号：EP84900432.0

申请日：1983-12-12

Applicant: Hughes Aircraft Company

Inventor： CHEN, John, Y.

IPC: H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L29/32 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/3221 ,  H01L27/0921

Abstract: Structure de dispositif CMOS de densité élevée (6) essentiellement immune au verrouillage et procédé de fabrication de la structure (6). Celle-ci est obtenue en créant une région de puits (14) dans une surface d'un substrat (12) et adjacente à la surface, la région de puits (14) ayant un profil de densité de dopage rétrograde multiple, et en aménageant des régions de source et de drain (18, 20) dans le puits (14) et adjacentes à la surface du substrat (12), les régions de source et de drain (18, 20) ayant une densité supérieure à la moyenne de défauts résiduels dans ladite région de puits (14), la densité plus grande que la moyenne de défauts résiduels étant généralement associée aux portions les plus profondes des régions de source et de drain (18, 20) et aux portions immédiatement sous-jacentes de ladite région de puits (14), respectivement.

公开(公告)号：EP0097533A3

公开(公告)日：1985-05-29

申请号：EP83303587

申请日：1983-06-22

Applicant: FUJITSU LIMITED

Inventor： Yahano, Toshi c/o FUJITSU LIMITED

IPC: H01L21/265 ,  H01L21/268 ,  H01L29/08

CPC classification number: H01L21/2636 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/2686 ,  H01L29/0847

Abstract: In a method of manufacturing an MIS type semiconductor device, an impurity region (16') is formed by implanting ions into a substrate (11) using a plurality of implantation energies and dosages, such that the peak of impurity concentration in the region does not exceed the electrically active solubility of the impurity. The impurity region (16') is then irradiated by an energy beam to activate the implanted impurity (16a, 16b) without any substantial redistribution thereof.

公开(公告)号：EP0055408B1

公开(公告)日：1984-11-21

申请号：EP81110322.5

申请日：1981-12-11

Applicant: FUJITSU LIMITED

Inventor： Matsumoto, Takashi ,  Nakano, Motoo

IPC: H01L29/60 ,  G11C11/34

CPC classification number: H01L21/2652 ,  H01L29/7883

Abstract: An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.

公开(公告)号：EP0081804A3

公开(公告)日：1984-07-25

申请号：EP82111357

申请日：1982-12-08

Applicant: Siemens Aktiengesellschaft

Inventor： Schwabe, Ulrich, Dr. ,  Jacobs, Erwin, Dr.

IPC: H01L21/265 ,  H01L21/31 ,  H01L21/82 ,  H01L27/08

CPC classification number: H01L21/823892 ,  H01L21/033 ,  H01L21/2652 ,  H01L27/0928

公开(公告)号：EP0110656A2

公开(公告)日：1984-06-13

申请号：EP83307118.6

申请日：1983-11-21

Applicant: NEC CORPORATION

Inventor： Imamura, Toru

IPC: H01L27/10 ,  H01L21/82 ,  H01L21/265 ,  H01L21/306 ,  H01L27/02

CPC classification number: H01L21/76897 ,  H01L21/2652 ,  H01L27/10805 ,  H01L29/66181

Abstract: In a semiconductor device having a thin insulating film of 300 A or less in thickness on which a conductive layer is provided, the conductive layer is connected to the semiconductor substrate at a position outside the active regions. With such a structure, negative charges accumulated on the conductive layer during the reactive ion etching or ion implantation process can be easily discharged to the semiconductor substrate to prevent a dielectric breakdown of the thin insulating film. In the embodiment, the thin insulating film is a dielectric film of a MOS storage capacitor of a one-transistor type memory cell and the conductive layer is the upper electrode of the MOS capacitor.

公开(公告)号：EP0103767A2

公开(公告)日：1984-03-28

申请号：EP83108255.7

申请日：1983-08-22

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Ajima, Takashi ,  Ohshima, Jiro ,  Koshino, Yutaka

IPC: H01L21/265 ,  H01L21/316

CPC classification number: H01L21/02178 ,  H01L21/02263 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3162

Abstract: A method of producing a semiconductor device in which an alumina layer (21) is formed directly on a principal surface (20a) of a silicon substrate (20); aluminum (22A) and silicon (228) are ion-implanted through the alumina layer (21) into said substrate (20) and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases solid solubility limit of aluminum.

Abstract translation: 生产，在其中的氧化铝层（21）直接形成在硅衬底（20）的主面（20a）的半导体器件的方法; 铝（22A）和硅（22B）中离子注入通过氧化铝层（21）到所述衬底（20）和基片随后被退火。 离子注入硅产生更好的晶体结构和增加的铝的固溶极限。

公开(公告)号：EP0097533A2

公开(公告)日：1984-01-04

申请号：EP83303587.6

申请日：1983-06-22

Applicant: FUJITSU LIMITED

Inventor： Yahano, Toshi c/o FUJITSU LIMITED

IPC: H01L21/265 ,  H01L21/268 ,  H01L29/08

CPC classification number: H01L21/2636 ,  H01L21/2652 ,  H01L21/268 ,  H01L21/2686 ,  H01L29/0847

Abstract: In a method of manufacturing an MIS type semiconductor device, an impurity region (16') is formed by implanting ions into a substrate (11) using a plurality of implantation energies and dosages, such that the peak of impurity concentration in the region does not exceed the electrically active solubility of the impurity. The impurity region (16') is then irradiated by an energy beam to activate the implanted impurity (16a, 16b) without any substantial redistribution thereof.

Abstract translation: 在制造MIS型半导体器件的方法中，通过使用多种注入能量和剂量将离子注入到衬底（11）中形成杂质区域（16分钟），使得该区域中杂质浓度的峰值不 超过杂质的电活性溶解度。 然后通过能量束照射杂质区（16分钟），以激活注入的杂质（16a，16b），而没有任何实质的再分布。

公开(公告)号：EP0072967A3

公开(公告)日：1983-11-16

申请号：EP82107239

申请日：1982-08-10

Applicant: Siemens Aktiengesellschaft

Inventor： Schwabe, Ulrich, Dr. ,  Jacobs, Erwin, Dr. ,  Scheibe, Adolf, Dr.

IPC: H01L21/82 ,  H01L21/28 ,  H01L21/265

CPC classification number: H01L21/823864 ,  H01L21/2652 ,  H01L27/0688

公开(公告)号：EP0090161A2

公开(公告)日：1983-10-05

申请号：EP83101406.3

申请日：1983-02-14

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： Müller, Wolfgang, Dr.

IPC: H01L27/10 ,  G11C11/24 ,  H01L21/76

CPC classification number: H01L27/10844 ,  H01L21/033 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/76216

Abstract: Die Erfindung betrifft ein Verfahren zum Herstellen von dynamischen Halbleiter-Speicherzellen mit wahlfreiem Zugriff (RAM) nach der Doppel-Polysilizium-Gate-Technologie, bei dem die Isolation benachbarter aktiver Bereiche durch Dickoxidbereiche (2) nach der bekannten LOCOS-Technologie erfolgt und bei dem zur Erhöhung der Zellkapazität in den Speicherbereich unter Verwendung einer Fotolackmaske (4) eine Bor (6) und Arsen-lonenimplantation (7) durchgeführt wird. Erfindungsgemäß wird zur Erhöhung der Packungsdichte im Prozeßverlauf die Oxiddicke (2, 2a) im Speicherbereich/Dickoxidtransistorbereich sowohl axial als auch lateral (L v ) durch Abätzen reduziert. Das Verfahren wird verwendet bei der Herstellung hochintegrierter Si 2 -Gate-RAM-Speicher.

Abstract translation: 本发明涉及一种方法，用于制造具有双多晶硅栅极技术之后的随机存取存储器（RAM）的动态半导体存储单元，其中，相邻的有源区由厚氧化物区域中的隔离（2）通过公知的LOCOS技术，并且其中制备 执行使用光致抗蚀剂掩模（4），以增加在所述存储器区域中的电池容量硼（6）和砷离子注入（7）。 根据本发明的氧化物厚度（2，2a）中是沿轴向和横向（LV）由用于在存储区/ Dickoxidtransistorbereich增加该方法的过程中的填充密度蚀刻减小。 该方法是在高度集成的Si²栅极RAM的制造中使用。

公开(公告)号：EP0089265A2

公开(公告)日：1983-09-21

申请号：EP83400437.6

申请日：1983-03-04

Applicant: FAIRCHILD CAMERA & INSTRUMENT CORPORATION

Inventor： Crossley, Peter Anthony ,  Tsai, Nan-Hsiung

IPC: H01L21/265 ,  H01L21/82

CPC classification number: H01L21/2652 ,  H01L21/2658 ,  H01L21/8238

Abstract: A method of fabricating a CMOS device is provided for patterning the gates and protecting them during ion implantation.
A metal layer (20) is sandwiched between the gate material layer (18) and the photoresist layer (22) that is used as a pattern mask for the gate material during etching. The photoresist pattern (22) masks the metal as it is etched, and the metal pattern (20M) masks the gate material as it is etched to form a gate pattern. The metal mask is left over the gates to serve as an ion implant stop mask. Two photoresist patterns are successively formed to cover the devices of one conductivity type while the opposite type device source and drain regions are implanted.
Then, the metal mask may be easily stripped without causing damage.

Abstract translation: 提供了一种用于图案化该栅极与离子植入期间保护它们制造CMOS器件的方法。 的金属层（20）被夹在所述栅极材料层（18）并没有被用作蚀刻过程中的栅极材料的掩模图案的光致抗蚀剂层（22）之间。 光致抗蚀剂图案（22）的掩模，因为它被蚀刻金属，并且该金属图案（20M）的掩模对栅极材料，因为它被蚀刻以形成栅极图案。 金属掩模剩下的栅极用以作为离子注入掩模停止，两个光致抗蚀剂图案被连续地形成，以覆盖一导电型的设备，而相反类型的器件源和漏区注入。 然后，将金属掩模可以容易地剥离而不损坏。